Генерация кода из модели с вложенными подсистемами.

`timescale 1ns/1ps

module model_RX_tb;
  reg clock;
  reg reset;
  wire io_Out3;
  wire [7:0] io_Out1;
  wire [7:0] io_Out2;

  model_RX dut (
    .clock(clock),
    .reset(reset),
    .io_Out3(io_Out3),
    .io_Out1(io_Out1),
    .io_Out2(io_Out2)
  );
  integer file;
  
  always #5 clock = ~clock;
  
  initial begin
    clock = 0;
    reset = 1;
    file = $fopen("output.txt", "w");
    #10 reset = 0;
    #1000;
    $fclose(file);
    $finish;
  end
  
  always @(posedge clock) begin
    if (!reset) begin
      $fdisplay(file, "%0t %b %h %h", $time, io_Out3, io_Out1, io_Out2);
    end
  end
endmodule