Счётчик Verilog

module count_Count(
  input         clock,
                reset,
  input  [31:0] io_Step,
                io_Limit_max,
  input         io_Reset,
  output [31:0] io_Cnt
);

  reg  [31:0] UnitDelay_state;
  wire [31:0] Switch =
    $signed(UnitDelay_state) > $signed(io_Limit_max) | io_Reset ? 32'h0 : UnitDelay_state;
  always @(posedge clock) begin
    if (reset)
      UnitDelay_state <= 32'h0;
    else
      UnitDelay_state <= io_Step + Switch;
  end // always @(posedge)
  assign io_Cnt = Switch;
endmodule

module testbench;
  reg clock;
  reg reset;
  reg [31:0] io_Step;
  reg [31:0] io_Limit_max;
  reg io_Reset;
  wire [31:0] io_Cnt;
  
  // Instantiate the module under test
  count_Count dut (
    .clock(clock),
    .reset(reset),
    .io_Step(io_Step),
    .io_Limit_max(io_Limit_max),
    .io_Reset(io_Reset),
    .io_Cnt(io_Cnt)
  );
  
  // Clock generation
  always #5 clock = ~clock;
  
  // Test sequence
  initial begin
    // Initialize signals
    clock = 0;
    reset = 1;
    io_Step = 3;
    io_Limit_max = 27;
    io_Reset = 0;
    
    // Display header
    $display("tStep\tLimit\tCnt");
    $monitor(io_Step, io_Limit_max, io_Cnt);
    
    // Apply reset
    #10 reset = 0;
    
    // Run simulation until counter wraps around
    #200;
    $finish;
  end
endmodule