Генерация кода из модели с вложенными подсистемами.
Author
/* Code generated by Engee
* Model name: model.engee
* Code generator: release-1.1.22
* Date: Wed Sep 10 06:27:06 2025 GMT
*/
module model_RX(
input clock,
reset,
output io_Out3,
output [7:0] io_Out1,
io_Out2
);
reg UnitDelay_1_state;
reg UnitDelay_13_state;
reg UnitDelay_state;
reg UnitDelay_1_1_state;
reg UnitDelay_2_state;
reg UnitDelay_3_state;
reg UnitDelay_4_state;
reg UnitDelay_13_1_state;
reg UnitDelay_14_state;
reg UnitDelay_5_state;
reg UnitDelay_6_state;
reg UnitDelay_14_1_state;
reg UnitDelay_7_state;
reg UnitDelay_8_state;
reg UnitDelay_9_state;
reg UnitDelay_10_state;
reg UnitDelay_11_state;
reg [3:0] UnitDelay_12_state;
reg [3:0] UnitDelay_13_2_state;
reg [3:0] UnitDelay_14_2_state;
reg [3:0] UnitDelay_15_state;
reg [3:0] UnitDelay_16_state;
reg [3:0] UnitDelay_17_state;
reg [3:0] UnitDelay_18_state;
reg [3:0] UnitDelay_19_state;
reg [3:0] UnitDelay_20_state;
reg [3:0] UnitDelay_21_state;
reg [3:0] UnitDelay_22_state;
reg [3:0] UnitDelay_23_state;
reg [3:0] UnitDelay_24_state;
reg [3:0] UnitDelay_25_state;
reg [3:0] UnitDelay_26_state;
reg [3:0] UnitDelay_27_state;
reg [3:0] UnitDelay_28_state;
reg [3:0] UnitDelay_29_state;
reg [3:0] UnitDelay_30_state;
reg [3:0] UnitDelay_31_state;
wire LogicalOperator = UnitDelay_13_state ^ UnitDelay_14_state;
wire LogicalOperator_1 = UnitDelay_1_state ^ UnitDelay_14_1_state;
wire [2:0] _IdxAccum_T_2 =
{1'h0, LogicalOperator, 1'h0} + {2'h0, LogicalOperator_1} + 3'h1;
wire _tmp6_T = _IdxAccum_T_2 == 3'h2;
wire _constellation_selector_im_T = _IdxAccum_T_2 == 3'h1;
wire [3:0] _constellation_selector_re_new_T_1 =
_constellation_selector_im_T | ~(_tmp6_T | _IdxAccum_T_2 == 3'h3) ? 4'h6 : 4'hA;
wire [3:0] _constellation_selector_im_new_T_1 =
_constellation_selector_im_T | _tmp6_T ? 4'h6 : 4'hA;
wire [10:0] _Gain_1_new_T_1 =
{{7{_constellation_selector_re_new_T_1[3]}}, _constellation_selector_re_new_T_1}
* 11'h7FF;
wire [10:0] _Gain_1_1_new_T_1 =
{{7{_constellation_selector_im_new_T_1[3]}}, _constellation_selector_im_new_T_1}
* 11'h7FF;
wire [10:0] _Gain_3_new_T_1 =
{{7{UnitDelay_14_2_state[3]}}, UnitDelay_14_2_state} * 11'h7FE;
wire [10:0] _Gain_3_1_new_T_1 =
{{7{UnitDelay_15_state[3]}}, UnitDelay_15_state} * 11'h7FE;
wire [10:0] _Gain_5_new_T_1 =
{{7{UnitDelay_19_state[3]}}, UnitDelay_19_state} * 11'h7FE;
wire [10:0] _Gain_5_1_new_T_1 =
{{7{UnitDelay_18_state[3]}}, UnitDelay_18_state} * 11'h7FE;
wire [10:0] _Gain_6_new_T_1 = {{7{UnitDelay_21_state[3]}}, UnitDelay_21_state} * 11'h30;
wire [10:0] _Gain_6_1_new_T_1 =
{{7{UnitDelay_20_state[3]}}, UnitDelay_20_state} * 11'h30;
wire [10:0] _Gain_7_new_T_1 =
{{7{UnitDelay_22_state[3]}}, UnitDelay_22_state} * 11'h7FE;
wire [10:0] _Gain_7_1_new_T_1 =
{{7{UnitDelay_23_state[3]}}, UnitDelay_23_state} * 11'h7FE;
wire [10:0] _Gain_9_new_T_1 =
{{7{UnitDelay_27_state[3]}}, UnitDelay_27_state} * 11'h7FE;
wire [10:0] _Gain_9_1_new_T_1 =
{{7{UnitDelay_26_state[3]}}, UnitDelay_26_state} * 11'h7FE;
wire [10:0] _Gain_11_new_T_1 =
{{7{UnitDelay_30_state[3]}}, UnitDelay_30_state} * 11'h7FF;
wire [10:0] _Gain_11_1_new_T_1 =
{{7{UnitDelay_31_state[3]}}, UnitDelay_31_state} * 11'h7FF;
always @(posedge clock) begin
if (reset) begin
UnitDelay_1_state <= 1'h0;
UnitDelay_13_state <= 1'h0;
UnitDelay_state <= 1'h0;
UnitDelay_1_1_state <= 1'h0;
UnitDelay_2_state <= 1'h0;
UnitDelay_3_state <= 1'h0;
UnitDelay_4_state <= 1'h0;
UnitDelay_13_1_state <= 1'h1;
UnitDelay_14_state <= 1'h0;
UnitDelay_5_state <= 1'h0;
UnitDelay_6_state <= 1'h0;
UnitDelay_14_1_state <= 1'h1;
UnitDelay_7_state <= 1'h0;
UnitDelay_8_state <= 1'h0;
UnitDelay_9_state <= 1'h0;
UnitDelay_10_state <= 1'h1;
UnitDelay_11_state <= 1'h0;
UnitDelay_12_state <= 4'h0;
UnitDelay_13_2_state <= 4'h0;
UnitDelay_14_2_state <= 4'h0;
UnitDelay_15_state <= 4'h0;
UnitDelay_16_state <= 4'h0;
UnitDelay_17_state <= 4'h0;
UnitDelay_18_state <= 4'h0;
UnitDelay_19_state <= 4'h0;
UnitDelay_20_state <= 4'h0;
UnitDelay_21_state <= 4'h0;
UnitDelay_22_state <= 4'h0;
UnitDelay_23_state <= 4'h0;
UnitDelay_24_state <= 4'h0;
UnitDelay_25_state <= 4'h0;
UnitDelay_26_state <= 4'h0;
UnitDelay_27_state <= 4'h0;
UnitDelay_28_state <= 4'h0;
UnitDelay_29_state <= 4'h0;
UnitDelay_30_state <= 4'h0;
UnitDelay_31_state <= 4'h0;
end
else begin
UnitDelay_1_state <= UnitDelay_13_1_state;
UnitDelay_13_state <= UnitDelay_10_state;
UnitDelay_state <= UnitDelay_1_1_state;
UnitDelay_1_1_state <= UnitDelay_9_state;
UnitDelay_2_state <= UnitDelay_11_state;
UnitDelay_3_state <= UnitDelay_5_state;
UnitDelay_4_state <= UnitDelay_2_state;
UnitDelay_13_1_state <= UnitDelay_8_state;
UnitDelay_14_state <= UnitDelay_13_state;
UnitDelay_5_state <= UnitDelay_4_state;
UnitDelay_6_state <= UnitDelay_3_state;
UnitDelay_14_1_state <= UnitDelay_1_state;
UnitDelay_7_state <= UnitDelay_6_state;
UnitDelay_8_state <= LogicalOperator_1;
UnitDelay_9_state <= UnitDelay_7_state;
UnitDelay_10_state <= LogicalOperator;
UnitDelay_11_state <= 1'h1;
UnitDelay_12_state <= _constellation_selector_re_new_T_1;
UnitDelay_13_2_state <= _constellation_selector_im_new_T_1;
UnitDelay_14_2_state <= UnitDelay_12_state;
UnitDelay_15_state <= UnitDelay_13_2_state;
UnitDelay_16_state <= UnitDelay_15_state;
UnitDelay_17_state <= UnitDelay_14_2_state;
UnitDelay_18_state <= UnitDelay_16_state;
UnitDelay_19_state <= UnitDelay_17_state;
UnitDelay_20_state <= UnitDelay_18_state;
UnitDelay_21_state <= UnitDelay_19_state;
UnitDelay_22_state <= UnitDelay_21_state;
UnitDelay_23_state <= UnitDelay_20_state;
UnitDelay_24_state <= UnitDelay_23_state;
UnitDelay_25_state <= UnitDelay_22_state;
UnitDelay_26_state <= UnitDelay_24_state;
UnitDelay_27_state <= UnitDelay_25_state;
UnitDelay_28_state <= UnitDelay_26_state;
UnitDelay_29_state <= UnitDelay_27_state;
UnitDelay_30_state <= UnitDelay_29_state;
UnitDelay_31_state <= UnitDelay_28_state;
end
end // always @(posedge)
assign io_Out3 = UnitDelay_state;
assign io_Out1 =
_Gain_1_new_T_1[10:3] + {8{UnitDelay_12_state[3]}} + _Gain_3_new_T_1[10:3]
+ {{6{UnitDelay_17_state[3]}}, UnitDelay_17_state[3:2]} + _Gain_5_new_T_1[10:3]
+ _Gain_6_new_T_1[10:3] + _Gain_7_new_T_1[10:3]
+ {{6{UnitDelay_25_state[3]}}, UnitDelay_25_state[3:2]} + _Gain_9_new_T_1[10:3]
+ {8{UnitDelay_29_state[3]}} + _Gain_11_new_T_1[10:3];
assign io_Out2 =
_Gain_1_1_new_T_1[10:3] + {8{UnitDelay_13_2_state[3]}} + _Gain_3_1_new_T_1[10:3]
+ {{6{UnitDelay_16_state[3]}}, UnitDelay_16_state[3:2]} + _Gain_5_1_new_T_1[10:3]
+ _Gain_6_1_new_T_1[10:3] + _Gain_7_1_new_T_1[10:3]
+ {{6{UnitDelay_24_state[3]}}, UnitDelay_24_state[3:2]} + _Gain_9_1_new_T_1[10:3]
+ {8{UnitDelay_28_state[3]}} + _Gain_11_1_new_T_1[10:3];
endmodule