Возможности генерации кода Verilog

//! BlockType = :Product
//! TargetLang = :Chisel

//! @Definitions
val $(output(1)) = Wire($(show_chisel_type(output(1))))
/*! @Step
function cast(sig)
    ".asTypeOf(FixedPoint($(sig.ty.bits).W,$(sig.ty.fractional_bits).BP))"
end
function maybe_cast_res_begin()
    output(1).ty.fractional_bits == 0 ? "(" : ""
end
function maybe_cast_res_end()
    output(1).ty.fractional_bits == 0 ? ").asSInt" : ""
end
*/
$(output(1)) := \
  $(maybe_cast_res_begin())\
    $(input(1))$(cast(input(1)))*$(input(2))$(cast(input(2)))\
  $(maybe_cast_res_end())