Счётчик Verilog

//! BlockType = :RelationalOperator
//! TargetLang = :Chisel

/*! #----------------------------------------------------# */
/*! @Definitions
function show_chisel_type(x::typ) :: String
	if x.bits == 1 && x.fractional_bits == 0
		out = "Bool()"
	elseif x.fractional_bits == 0
		out = (x.is_unsigned ? "U" : "S") * "Int($(x.bits).W)"
	else
		out = "FixedPoint($(x.bits).W,$(x.fractional_bits).BP)"
	end
	out
end
function show_chisel_type(x::signal) :: String
	base_type = show_chisel_type(x.ty)
	len = x.rows * x.cols
	len == 1 ? base_type : "Vec($(len), $(base_type))"
end
*/
val $(output(1)) = Wire($(show_chisel_type(output(1))))
/*! #----------------------------------------------------# */
/*! @Step
function patch_op(op)
    op == "==" ? "===" : op == "~=" ? "=/=" : op
end
function get_idx(len, blen)
    if len == 1
        return ""
    elseif len == blen
        return "(i)"
    else
        return "(i % $(len))"
    end
end
function maybe_zext(sig, sig2)
    if sig.ty.is_unsigned && !sig2.ty.is_unsigned
        return ".zext"
    end
    ""
end
function impl(sig1, sig2, op, out)
    dim0 = dim(out)
    dim1 = dim(sig1)
    dim2 = dim(sig2)
    blen = lcm(dim1, dim2) # broadcasted length
    if blen == 1
        loop_decl = ""
    else
        loop_decl = "for (i <- 0 until $(blen)) "
    end
    "$(loop_decl)$(output(1))$(get_idx(dim0, blen)) := \
        $(sig1)$(get_idx(dim1, blen))$(maybe_zext(sig1, sig2)) \
         $(patch_op(op)) \
        $(sig2)$(get_idx(dim2, blen))$(maybe_zext(sig2, sig1))"
end
*/
$(impl(input(1), input(2), param.Operator, output(1)))
/*! #----------------------------------------------------# */