# CIC滤波器参数
name_model = "cic_$(round(Int, rand() * 10000))"
Path = (@__DIR__) * "/" * name_model * ".engee"
println("Path: $Path")

R = 5  # 抽取系数
FIXED_POINT_TYPE = "fixdt(1, 16, 14)"

engee.create(name_model) 
engee.add_block("/Basic/Ports & Subsystems/In1", name_model*"/")
engee.add_block("/Basic/Ports & Subsystems/Out1", name_model*"/")
engee.set_param!(name_model*"/In1",
    "OutDataTypeStr" => "Fixed-point",
    "OutDataTypeStrFixed" => FIXED_POINT_TYPE)
engee.add_block("/Basic/Math Operations/Add", name_model*"/Integrator_Add")
engee.add_block("/Basic/Discrete/Unit Delay", name_model*"/Integrator_Delay")
engee.set_param!(name_model*"/Integrator_Add",
    "Inputs" => "+-",  
    "OutDataTypeStr" => "Fixed-point",
    "OutDataTypeStrFixed" => FIXED_POINT_TYPE)
engee.add_line("In1/1", "Integrator_Add/1")
engee.add_line("Integrator_Add/1", "Integrator_Delay/1")
engee.add_line("Integrator_Delay/1", "Integrator_Add/2")
prev_delay = "Integrator_Delay"
for i in 1:R
    delay_name = "Delay_$i"
    engee.add_block("/Basic/Discrete/Unit Delay", name_model*"/"*delay_name)
    if i == 1
        engee.add_line("Integrator_Delay/1", delay_name*"/1")
    else
        prev_delay_name = "Delay_$(i-1)"
        engee.add_line(prev_delay_name*"/1", delay_name*"/1")
    end
    prev_delay = delay_name
end
engee.add_block("/Basic/Math Operations/Add", name_model*"/Comb_Add")
engee.set_param!(name_model*"/Comb_Add",
    "OutDataTypeStr" => "Fixed-point",
    "OutDataTypeStrFixed" => FIXED_POINT_TYPE)
engee.add_line("Integrator_Delay/1", "Comb_Add/1") 
engee.add_line("Delay_$R/1", "Comb_Add/2")     
engee.add_line("Comb_Add/1", "Out1/1")
engee.save(Path)
model = engee.load(Path, force=true)

function run_model( name_model)
    Path = (@__DIR__) * "/" * name_model * ".engee"
    if name_model in [m.name for m in engee.get_all_models()] # 检查将模型加载到内核的条件
        model = engee.open( name_model ) # 打开模型
        model_output = engee.run( model, verbose=true ); # 启动模型
    else
        model = engee.load( Path, force=true ) # 上传模型
        model_output = engee.run( model, verbose=true ); # 启动模型
        engee.close( name_model, force=true ); # 关闭模型
    end
    sleep(0.1)
    return model_output
end
run_model("cic_5") # 启动模型。

Valid_out = collect(simout["cic_5/CIC_decim/Gen_valid/Logical Operator.1"]).value
Data_out = collect(simout["cic_5/CIC_decim/开关。1"]).value
Data_CIC = collect(simout["cic_5/CIC_decim/CIC.Out1"]).value

p1 = plot(Data_out, label="Data_out", linewidth=2, ylabel="意义", title="CIC滤波器的输出", legend=:topright)
plot!(p1, Data_CIC, label="Data_CIC",  linewidth=2, linestyle=:dash)
p2 = plot(Valid_out, label="Valid_out", linewidth=2, ylabel="有效信号", title="有效信号(有效)", color=:red, legend=:topright) 
plot(p1, p2, layout=(@layout [a; b]), size=(800, 600))

# 使用代码定义目录的路径
prj_path = joinpath(@__DIR__, "cic_5_CIC_decim_code")
# 检查目录的存在
if !isdir(prj_path)
    error("未找到目录：pr prj_path")
end
# 暂时移动到项目目录
cd(prj_path) do
    # 汇编
    run(`iverilog -o sim tb_cic.v cic_5_CIC_decim.v CIC.v Gen_valid.v`)
    # 运行模拟
    run(`vvp sim`)
    
    # 从文件读取结果
    if isfile("results.txt")
        lines = readlines("results.txt")
        out_model = Float64[]
        for line in lines
            if occursin(r"^\d+\t", line)  # 我们正在寻找带有数据的行（以数字开始）
                parts = split(line, "\t")
                if length(parts) >= 2
                    push!(out_model, parse(Float64, parts[2]))
                end
            end
        end
        # 表头的输出
        println("非也。.\T值")
        println("--\t-------")
        # 仅输出前8个值
        for i in 1:min(8, length(out_model))
            println("$i\t$(out_model[i])")
        end
        # 显示总共有多少条记录
        println("\n文件中的条目数：$(length(out_model))")
    else
        println("文件结果。txt未找到！")
    end
end