Возможности генерации кода Verilog
Author
run_model(name) = begin
path = (@__DIR__) * "/" * name * ".engee"
m = name in [m.name for m in engee.get_all_models()] ?
engee.open(name) : engee.load(path, force=true)
out = engee.run(m, verbose=true)
name in [m.name for m in engee.get_all_models()] || engee.close(name, force=true)
sleep(0.1)
out
end
function read_v(filename)
try
if !isfile(filename)
println("Файл $filename не найден!")
return
end
println("Содержимое файла $filename:")
println("="^50)
content = read(filename, String)
println(content)
catch e
println("Ошибка при чтении файла: ", e)
end
end
function extract_verilog_parameters(output::String)
lines = split(output, '\n')
h4_line = ""
h5_line = ""
for line in lines
if startswith(line, "h=4:")
h4_line = line
elseif startswith(line, "h=5:")
h5_line = line
end
end
h4_vals = [parse(Float64, m.captures[1]) for m in eachmatch(r"=([\d.]+)", h4_line)]
h5_vals = [parse(Float64, m.captures[1]) for m in eachmatch(r"=([\d.]+)", h5_line)]
m_verilog = h4_vals[2]
P_verilog = h4_vals[3]
S4_verilog = h4_vals[4]
S5_verilog = h5_vals[4]
return (m_verilog, P_verilog, S4_verilog, S5_verilog)
end
if !isfile("$(@__DIR__)/tb.v")
tb_content = """
module tb_trapeze;
reg clk=0,rst=1;
reg[15:0] a=5<<8,b=7<<8,h=4<<8,c=3<<8,d=4<<8;
wire[15:0] m,P,S;
model_trapeze_calculator dut(clk,rst,a,b,h,c,d,m,P,S);
always #5 clk=~clk;
initial begin
#15 rst=0;
#10; // h=4
\$display("h=4: m=%0.2f P=%0.2f S=%0.2f",
\$itor(\$signed(m))/256.0,
\$itor(\$signed(P))/256.0,
\$itor(\$signed(S))/256.0);
h=5<<8;
#10; // h=5
\$display("h=5: m=%0.2f P=%0.2f S=%0.2f",
\$itor(\$signed(m))/256.0,
\$itor(\$signed(P))/256.0,
\$itor(\$signed(S))/256.0);
#10 \$finish;
end
endmodule
"""
write("$(@__DIR__)/tb.v", tb_content)
end