Возможности генерации кода Verilog

module tb_trapeze;
reg clk=0,rst=1;
reg[15:0] a=5<<8,b=7<<8,h=4<<8,c=3<<8,d=4<<8;
wire[15:0] m,P,S;
model_trapeze_calculator dut(clk,rst,a,b,h,c,d,m,P,S);
always #5 clk=~clk;
initial begin
    #15 rst=0;
    #10; // h=4
    $display("h=4: m=%0.2f P=%0.2f S=%0.2f", 
            $itor($signed(m))/256.0,
            $itor($signed(P))/256.0,
            $itor($signed(S))/256.0);
    h=5<<8;
    #10; // h=5
    $display("h=5: m=%0.2f P=%0.2f S=%0.2f", 
            $itor($signed(m))/256.0,
            $itor($signed(P))/256.0,
            $itor($signed(S))/256.0);
    #10 $finish;
end
endmodule