Возможности генерации кода Verilog

module model_trapeze_calculator(
  input         clock,
                reset,
  input  [15:0] io_a,
                io_b,
                io_h,
                io_c,
                io_d,
  output [15:0] io_m,
                io_P,
                io_S
);

  wire [15:0] __1Accum_T = io_a + io_b;
  wire [23:0] _Product_new_T_1 =
    {{9{__1Accum_T[15]}}, __1Accum_T[15:1]} * {{8{io_h[15]}}, io_h};
  assign io_m = {__1Accum_T[15], __1Accum_T[15:1]};
  assign io_P = __1Accum_T + io_c + io_d;
  assign io_S = _Product_new_T_1[23:8];
endmodule