PN Sequence Generator

A linear feedback shift register (LFSR) implemented as a simple shift register generator (SSRG) is used to generate PN sequences. This type of shift register is also known as a Fibonacci implementation.

The polynomial defines the feedbacks of the shift register. It is a primitive binary polynomial . For the quotient , where is from 0 to , the quotient is 1 if there is a link from to the adder. The leading term, , and the constant term, , of the generating polynomial must be equal to 1 because the polynomial must be primitive. At each time step, all registers, , in the generator update their values according to the value of the incoming arrow in the shift register. The adders perform addition modulo 2. The output of the LFSR reflects the sum of all connections in the mask vector .

This table shows two sets of parameters values that correspond to the generating polynomial .

The implementation orients the shift registers from left to right, with the generating polynomial ( ), initial states, and mask output defined in descending order. Specifically, .

When trying to model and compare results from the literature, you need to understand whether your source uses the same convention or a mirror image of that convention and are defined in ascending order.

To shift the starting point of a PN sequence, specify the Output mask vector (or scalar shift value) parameters as:

For example, if the degree of the generating polynomial is 4, then the mask vector corresponding to , is [0 1 0 0 0] which represents the polynomial .

Before resetting the sequence generator, the Reset on nonzero input parameters must be checked to enable the Rst input port. Assume that the PN Sequence Generator block outputs [1 0 0 0 1 1 0 1 1 0 1 1 1 1] when there is no reset. This table shows the effect of the specified parameter values on the output of the PN Sequence Generator block.

In the case of no reset, the block outputs the sequence without reset. For the cases of scalar and vector reset signal, the block supplies a reset signal [0 0 0 0 0 1 0 0 0 0 0 0 0 0] to the Rst port. Since the fourth bit of the reset signal is 1 and Sample time is 1, the block resets the sequence output in the fourth bit.

To generate a sequence of maximum length for a generating polynomial of degree , set the Generator polynomial parameters to the value from the following table. The maximum length of the sequence is .

For details on the shift register configurations that these polynomials represent, see [1].

The time between output updates is equal to the product of the Samples per frame and Sample time parameters. For example, if Sample time and Samples per frame are equal to 1, the block outputs one sample every second. If you increase Samples per frame to 10, the block will output a 10 by 1 vector every 10 seconds. This synchronisation ensures that the equivalent output rate is independent of the Samples per frame parameters.