Codeword frame error detector according to the generating polynomial.
blockType: GeneralCRCSyndromeDetector
Path in the library:
/Communication Systems/Error Detection And Correction/CRC/General CRC Syndrome Detector
Description
The General CRC Syndrome Detector block calculates cyclic redundancy checksums (CRC) for received codeword frames. For correct detection of errors in the communication channel it is necessary to coordinate parameters settings of the General CRC Syndrome Detector block with the paired General CRC Generator block.
An output frame returned as a binary vector-column that inherits the data type of the input signal type. The output frame contains the received codeword with checksums removed.
The length of the output frame is bits, where is the size of the received codeword, is the number of checksums in the frame, and is the degree of the generating polynomial.
A checksum error signal returned as a binary vector-column that inherits the data type of the input signal.
The length of Err is equal to the value of Checksums per frame. For each checksum calculation, the value of the 0 element in Err indicates no checksum error, and the value of the 1 element in Err indicates a checksum error.
The generating polynomial for the CRC algorithm, specified in one of the following ways:
Polynomial symbol vector. Example: .
A binary string vector that represents the coefficients of the generator polynomial in descending order of power. The length of this vector is (), where is the degree of the generating polynomial. Example: [1 1 0 1 1] represents the polynomial .
A vector of integer strings containing the exponents for the non-zero terms of the polynomial in descending order. Example: [3 2 0 0] represents a polynomial .
By default, the CRC-16-CCITT generating polynomial is used.
This table lists some commonly used generating polynomials.
Example: z^7 + z^2 + 1', [1 0 0 0 0 0 0 0 1 0 1 0 1] and [7 2 0 0] represent the same polynomial, .
Default value
z^16 + z^12 + z^5 + 1
Program usage name
GeneratorPolynomial
Tunable
No
Evaluatable
Yes
#Initial states —
initial states of the internal shift register
Details
Initial states of the internal shift register specified as a binary scalar or a binary vector-string with length equal to the degree of the generating polynomial.
The scalar value is expanded into a string vector with length equal to the degree of the generating polynomial.
Default value
0
Program usage name
InitialStates
Tunable
No
Evaluatable
Yes
#Direct method —
inclusion of a direct algorithm for checksum calculation
Logical
Details
Select this check box to use the direct algorithm to calculate the CRC checksum. If unchecked, the unit uses an indirect algorithm to calculate the CRC checksum.
Default value
false (switched off)
Program usage name
DirectMethod
Tunable
No
Evaluatable
No
#Reflect input bytes —
switching on the display of input bytes
Logical
Details
Select this check box to flip the input data byte-by-byte before entering data into the shift register.
If the Reflect input bytes parameter is checked, the length of the input frame divided by the value of the Checksums per frame parameter must be an integer multiple of 8.
If the Reflect input bytes parameters is unchecked, the block does not flip the input data.
Default value
false (switched off)
Program usage name
ReflectInputBytes
Tunable
No
Evaluatable
No
#Reflect checksums before final XOR —
Enable display of checksums before the last XOR operation
Logical
Details
Select this checkbox to flip the CRC checksums around their centres after the input data has passed completely through the shift register.
If the Reflect checksums before final XOR parameters are unchecked, the block does not flip the CRC checksums.
The last XOR operation specified as a binary scalar or binary string vector with length equal to the degree of the generating polynomial.
The XOR operation is performed by usage of the Final XOR parameters value as a CRC checksum before adding the CRC to the input data. The scalar value is expanded to a string vector with length equal to the degree of the generating polynomial.
The 0 value of the Final XOR parameters is equivalent to no XOR operation.
Default value
0
Program usage name
FinalXOR
Tunable
No
Evaluatable
Yes
#Checksums per frame —
number of checksums calculated for each frame
Int64 integer
Details
The number of checksums calculated for each frame, specified as a positive integer.
Default value
1
Program usage name
ChecksumsPerFrame
Tunable
No
Evaluatable
Yes
Algorithms
Direct and indirect CRC algorithms
The General CRC Syndrome Detector supports CRC checksum generation using indirect and direct CRC conversion algorithms.
Indirect CRC algorithm
The indirect CRC conversion algorithm takes a binary data vector corresponding to the polynomial , and adds a checksum of bits corresponding to the polynomial .
Cascading the input vector and checksum corresponds to the polynomial , since multiplication by corresponds to shifting the input vector a few bits to the left. The algorithm selects the checksum such that is a multiple of a predetermined polynomial of degree , called the generating polynomial.
The algorithm divides by , and sets the checksum equal to the binary vector corresponding to the remainder. That is, if , where is a polynomial of degree less than , then the checksum is the binary vector corresponding to . If necessary, the algorithm adds zeros to the checksum to make it of length .
The CRC generation function, which implements the transmission phase of the CRC algorithm, does the following:
Shifts the input data vector to the left by bits and divides the corresponding polynomial by .
Sets a checksum equal to a binary vector of length , corresponding to the remainder of step 1.
Adds the checksum to the input vector. The result is the output vector. The CRC detection function calculates the checksum for the entire input vector as described above.
The CRC algorithm uses binary vectors to represent binary polynomials in descending order of strength. For example, the vector [1 1 0 1 1] represents the polynomial .
The bits enter the linear feedback shift register (LFSR) from the low index bit to the high index bit. The sequence of input message bits represents the coefficients of the message polynomial in descending order of power. The message vector is augmented with zeros , to clear the LFSR, where is the degree of the generating polynomial. If the output of the left stage register d(1) is 1, the bits in the shift register are XORed with the coefficients of the generating polynomial. When the augmented message sequence passes completely through the LFSR, the register contains a checksum [d(1) d(2) … d(r)]. This is an implementation of binary long division, in which the message sequence is the divisor (numerator) and the polynomial is the dividend (denominator). The CRC checksum is the remainder of the division operation.
Direct CRC algorithm
This block diagram shows the direct CRC algorithm.
Where Message Block Input is , and Code Word Output is
The initial stage of direct CRC coding occurs when the three switches are in the position . The algorithm feeds the encoder with the message bits . These bits are the first bits of the output codeword. At the same time, the algorithm sends bits to the linear feedback shift register (LFSR). When the system has fully transferred -th bits of the message to the LFSR, the switches move to . Here the LFSR contains the mathematical residue from dividing the polynomial. These bits are shifted out of the LFSR and are the remaining bits (checksum) at the output of the codeword.
CRC detector operation
The General CRC Syndrome Detector block outputs the frame of the received message and the checksum error vector according to the specified generating polynomial and the number of checksums in the frame.
The checksum bits are removed from each subframe so that the resulting length of the output frame is , where is the length of the received codeword column, is the number of checksums in the frame, and is the degree of the generating polynomial. The input frame should be a uniform multiple of .
For a particular initial state of the internal shift register:
The resulting codeword is divided into C equal-sized subframes.
CRC checksum is removed from each of subframes and compared with the checksum calculated for the received codeword subframes.
The output frame is assembled by combining the subframe bits with the subframes and then output as a column vector.
The checksum error is output as a binary column vector of length . The value of 0 element indicates that there is no error in the received subframe, and the value of 1 element indicates that there is an error in the received subframe.
For the scenario shown here, a 16-bit codeword with an error in the third bit is received, a generating polynomial is used to calculate the checksum , the initial state is 0, and the number of checksums per frame is 2.
The input frame is divided into two subframes of size 5, and checksums of size 3 are calculated and added to each subframe. The initial states are not shown because the initial state [0] does not affect the result of the CRC algorithm. The output frame of the transmitted codeword is 5 + 3 + 5 + 5 + 3 = 16 bits.