General CRC Generator
CRC code bit generator according to the generating polynomial.
Description
The General CRC Generator block generates cyclic redundancy check (CRC) bits for each frame of input data and appends them to the frame.
Ports
Input
#
IN_1
—
input signal
binary column vector
Details
Input signal specified as a binary column vector. The length of the input frame must be a multiple of the Checksums per frame parameter value.
| Data types |
|
| Complex numbers support |
No |
Output
#
OUT_1
—
output codeword frame
`binary column vector
Details
A codeword output frame returned as a binary vector-column that inherits the input signal output signal type. The output is the input data frames with CRC bit sequences appended to them.
The length of the output frame is , where is the size of the input frame, is the number of checksums in the frame, and is the degree of the generating polynomial.
| Data types |
|
| Complex numbers support |
No |
Parameters
Parameters
#
Generator polynomial —
generating polynomial
String
Details
The generating polynomial for the CRC algorithm, specified in one of the following ways:
-
A symbolic representation of the polynomial. Example:
z^3 + z^2 + 1. -
A binary vector whose elements specify the coefficients of the generating polynomial in descending order of power. The length of this vector is ( ), where is the degree of the generating polynomial. Example:
[1 1 0 1 1]represents the polynomial . -
A vector of integers containing the degrees of for the non-zero terms of the polynomial in descending order. Example:
[3 2 0 0]represents a polynomial .
By default, the CRC-16-CCITT generating polynomial is used.
This table lists some commonly used generating polynomials.
CRC algorithm name |
Generating polynomial |
CRC-32 |
|
CRC-24 |
|
CRC-16 |
|
CRC-16-CCITT |
|
Reversed CRC-16 |
|
CRC-8 |
|
CRC-4 |
|
Example: z^7 + z^2 + 1', [1 0 0 0 0 0 0 0 1 0 1 0 1] and [7 2 0 0] represent the same polynomial, .
| Default value |
|
| Program usage name |
|
| Tunable |
No |
| Evaluatable |
Yes |
# Initial states — initial states of the internal shift register
Details
Initial states of the internal shift register specified as a binary scalar or binary vector-string with length equal to the degree of the generating polynomial.
The scalar value is expanded into a vector-string with length equal to the degree of the generating polynomial.
| Default value |
|
| Program usage name |
|
| Tunable |
No |
| Evaluatable |
Yes |
#
Direct method —
inclusion of a direct algorithm for checksum calculation
Logical
Details
Select this check box to use the direct algorithm to calculate the CRC checksum. When unchecked, the unit uses an indirect algorithm to calculate the CRC checksum.
| Default value |
|
| Program usage name |
|
| Tunable |
No |
| Evaluatable |
No |
#
Reflect input bytes —
Enabling reflection of input bytes
Logical
Details
Select this check box to flip the input data byte-by-byte before entering the data into the shift register.
-
If the Reflect input bytes check box is selected, the input frame length divided by the Checksums per frame value must be an integer multiple of
8. -
If the Reflect input bytes parameter is unchecked, the block does not flip the input data.
| Default value |
|
| Program usage name |
|
| Tunable |
No |
| Evaluatable |
No |
#
Reflect checksums before final XOR —
enabling checksum reflection before the last XOR operation
Logical
Details
Select this checkbox to flip the CRC checksums around their centres after the input data has passed completely through the shift register.
-
If Reflect checksums before final XOR is unchecked, the block does not flip CRC checksums.
| Default value |
|
| Program usage name |
|
| Tunable |
No |
| Evaluatable |
No |
# Final XOR — last XOR operation
Details
The last XOR operation specified as a binary scalar or binary string vector with length equal to the degree of the generating polynomial.
The XOR operation is performed using the Final XOR parameter value with the calculated CRC checksum bits before adding them to the input data. The scalar value is expanded to a vector of strings with length equal to the degree of the generating polynomial.
-
The
0value of the Final XOR parameter is equivalent to no XOR operation.
| Default value |
|
| Program usage name |
|
| Tunable |
No |
| Evaluatable |
Yes |
#
Checksums per frame —
number of checksums calculated for each frame
Int64 integer
Details
The number of checksums calculated for each frame, specified as a positive integer.
| Default value |
|
| Program usage name |
|
| Tunable |
No |
| Evaluatable |
Yes |
Algorithms
Direct and indirect CRC algorithms
The General CRC Generator unit supports CRC checksum generation using the indirect or direct CRC algorithm.
Indirect CRC algorithm
The indirect CRC algorithm takes a binary data vector corresponding to the polynomial , and adds a checksum of bits corresponding to the polynomial .
Cascading the input vector and checksum corresponds to the polynomial , since multiplication by corresponds to shifting the input vector a few bits to the left. The algorithm chooses the checksum such that is a multiple of a predetermined polynomial of degree , called the generating polynomial.
The algorithm divides by , and sets the checksum equal to the binary vector corresponding to the remainder. That is, if , where is a polynomial of degree less than , then the checksum is the binary vector corresponding to . If necessary, the algorithm adds zeros to the checksum to make it of length .
The CRC generation function, which implements the transmission phase of the CRC algorithm, does the following:
-
Shifts the input data vector to the left by bits and divides the resulting polynomial by .
-
Sets the checksum equal to a binary vector of length , corresponding to the remainder of step 1.
-
Adds the checksum to the input vector. The result is the output vector.
The CRC detection function calculates the checksum for the entire input vector as described above.
The CRC algorithm uses binary vectors to represent binary polynomials in descending order of strength. For example, the vector [1 1 0 1 1] represents the polynomial .
The bits enter the linear feedback shift register (linear feedback shift register, LFSR) in order from the lowest bit to the highest bit. The sequence of input message bits represents the coefficients of the message polynomial in descending power order. The message vector is augmented with zeros to flush out the LFSR, where is the degree of the generating polynomial. If the output of the left register stage d(1) is 1, an XOR operation is performed on the bits of the shift register with the coefficients of the generating polynomial. When the augmented message sequence passes completely through the LFSR, a checksum [d(1) d(2) … d(r)] remains in the register. This is an implementation of binary long division, in which the message sequence is the divisor (numerator) and the polynomial is the divisor (denominator). The CRC checksum is the remainder of the division operation.
Direct CRC algorithm
The block diagram shows the direct CRC algorithm.
Here Message Block Input is , and Code Word Output is
The initial stage of direct CRC coding occurs when the three switches are in the position . The algorithm feeds the encoder with the message bits . These bits are the first bits of the output codeword. At the same time, the algorithm sends bits to the linear feedback shift register (LFSR). When the system has completely transferred all bits of the message to the LFSR, the switches move to . Here the LFSR contains the mathematical remainder from dividing the polynomial. These bits are shifted out of the LFSR and are the remaining bits (checksum) at the output of the codeword.
CRC generator operation
The CRC generator adds CRC checksums to the input frame according to the specified generating polynomial and number of checksums per frame.
For a given initial state of the internal shift register and checksums per input frame:
-
The input signal is divided into subframes of equal size.
-
Each of subframe corresponds to a prefix from the initial state vector.
-
A CRC algorithm is applied to each subframe.
-
The resulting checksums are added to the end of each subframe.
-
The subframes are combined and output as vector-columns. For the scenario shown here, a 10-bit frame is given as input, a generating polynomial calculates the CRC checksum, the initial state is
0, and the number of checksums per frame is2.
The input frame is divided into two subframes of size 5, and checksums of size 3 are computed and added to each subframe. The initial states are not shown because the initial state [0] does not affect the result of the CRC algorithm. The output frame of the transmitted codeword is 5 + 3 + 5 + 5 + 3 = 16 bits.
Literature
-
Sklar, Bernard. "Digital Communications: Fundamentals and Applications". Englewood Cliffs, N.J.: Prentice-Hall, 1988.
-
Wicker, Stephen B. "Error Control Systems for Digital Communication and Storage." Upper Saddle River, N.J.: Prentice Hall, 1995.