Engee documentation

Code Generation in Engee

Description

In the course Code Generation in Engee you will learn how to generate code from Engee models and subsystems in C and Verilog languages, verify the generated code using the C Function block, explore the Engee code generator options, ways to integrate code into an external development environment, and features of code generation for finite automata.

Each section contains a theoretical part, practical examples and self-study tasks.

Knowledge requirements: completion of the courses Welcome to Engee and Visual Simulation.

Total course time: ~3 hours.

Course program

Generating C code from Engee models

Generation of C code through the Engee graphical interface, internal functions and parameters in the generated code, description of generated files, integration into the external development environment, supported data types, multirate models, comments in the generated code, control of signal names are studied.

Code generation via command line and interactive script

Code generation using the command engee.generate_code() is studied. In the command line or in the script editor, examples of code generation for the smoothing lowpass filter model and the autopilot control system model are considered.

Code verification

Code verification is studied, which includes generating a script with Engee programmatic control commands and creating a verification model with a C Function block containing the generated C code.

Code generation for state machines

General information about state machines is given, the features of code generation for state machines are studied, an example of code generation for a blinking LED model based on state machines and the launch of the generated code on the STM32 microcontroller are considered.

Generation of Verilog code

General information about the Verilog language is given, the features of generating Verilog code for Engee models, the capabilities of the Verilog code generator, Verilog code verification are studied, an example of generating Verilog code for the PID controller model is considered, an overview of how to work with Verilog from the inside is given.