Support package for managing the RITM SDR USRP hardware platform
The article contains information necessary for use in Engee libraries Targets.RITM_SDR_API designed for remote control of the RITM SDRfootnote hardware platform:[SDR (Software Defined Radio) is a software—defined radio.] USRP[1] and data exchange over an Ethernet network. The requirements for the runtime environment, the connection procedure, the description of the application programming interface (API) and the register map of the main IP cores are given. note:[IP core is a hardware functional module within the FPGA/SNC, accessible by address space.].
Purpose and conditions of use
Library Targets.RITM_SDR_API It is designed to control the RITM SDR USRP hardware platform based on the Xilinx Zynq UltraScale+ system-on-chip and the ADRV9009 RF transceiver. Management is carried out through network interaction with the RITM SDR USRP control module.
The SDR USRP RITM provides operation in the range of 75 MHz – 6 GHz with an instantaneous band up to 450 MHz. Library Targets.RITM_SDR_API It is used in the development, debugging and testing of wireless communication and radar systems.
General information
Library Targets.RITM_SDR_API implements a set of strongly typed Julia language methods and macros for performing the following operations:
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establishing and terminating a TCP connection with the RITM SDR USRP control module;
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setting radio frequency and path parameters (frequency, attenuation, TX/RXfootnote modes:[TX /RX — transmission/reception channels.]);
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performing IP core reset and management procedures;
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transmission and reception of I/Q samples and service data.
Interaction with the RITM SDR USRP is performed through Engee Device Manager. The diagram of the component interaction is shown in the figure.

Execution conditions
For the library to work Targets.RITM_SDR_API required:
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RITM SDR USRP access to an Ethernet network;
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availability Engee Device Manager on the side of the control computer (when used according to the accepted architecture).
Default Network settings:
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IP address: SDR USRP —
192.168.2.70; -
TCP port —
12345.
Quick start
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Install or connect the Engee subsystem.Integration as shown in article.
engee.package.install("Engee-Device-Manager")Connection link: engee.com/prod/user/demo1234-user Install the client program: https://dl.kpm-ritm.ru/repo/Host-Device-Manager-v1.57-Windows.zip - For Windows https://dl.kpm-ritm.ru/repo/Host-Device-Manager-v1.57-Linux.zip - For Linux To get examples, run: engee.package.getdemos("Engee-Device-Manager") To run the server program, run: engee.package.start("Engee-Device-Manager") The 'Engee-Device-Manager' support package, version 'v1.57', has been successfully installed.engee.package.start("Engee-Device-Manager")"engee.com/prod/user/demo1234-user" -
Use the commands:
using Main.EngeeDeviceManager.Targets.RITM_SDR_API import Main.EngeeDeviceManager.Targets.RITM_SDR_API client = RITM_SDR_API.RITMClient("192.168.2.70") if !RITM_SDR_API.connect(client) println("Connection error") return end println("Server version: $(RITM_SDR_API.get_version(client))") RITM_SDR_API.disconnect(client)An example of the expected output to the console:
Connected to 192.168.2.70:12345 Server version: v5.1.5 Connection closed
For more information, see the article Getting started with the RITM SDR USRP
Application Programming Interface (API)
This section describes the macros and functions of the library. For each item, the name, prototype (if available in the source text) and purpose are indicated.
Logging Group
| Name | The prototype | Appointment |
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A macro for «quiet» logging without output to the console. Records data only if |
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The main switch of the logging system. Sets a global variable |
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The main macro for combined output. Converts the expression to a string, clears it, prints it to the console, and if logging is active, writes it to a timestamped log file. Example: |
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Prints a message to the console without a newline. It is used for interactive progress bars or displaying partial results in one line. |
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Logging session ends correctly. Adds a final entry, creates a cleaned-up version of the log file, and resets global variables. |
Service functions
| Name | The prototype | Appointment |
|---|---|---|
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Constructor of the main library object. Creates a structure with the following fields: the IP address of the control module, the TCP connection descriptor, and the sampling rate (by default). |
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Clearing string responses from the control module of control and non-printable characters. |
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Clearing the input buffer of the network socket. |
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Receiving binary data from the control module according to the established protocol. |
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Sending binary data to the control module using the established protocol. |
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A key low-level function for sending commands to the control module. Sends a command, waits for processing, reads and analyzes the response. |
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Secure disconnection. |
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Establishing a TCP connection with the control module. The port is fixed — |
Managing basic parameters
| Name | The prototype | Appointment |
|---|---|---|
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Request the calibration status of the system. |
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Request for the current frequency. |
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Request for a tabular value of receiver attenuation. |
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Measuring the power at the receiver input. |
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Request for the current status of the transceiver. |
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Request for transmitter attenuation. |
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Setting the carrier frequency of the transmitter and receiver. Checks the range, sends a command |
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Universal parameter setting. |
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Setting the tabular value of receiver attenuation. |
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Configuration of the transmitter and receiver channels using bit masks. |
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Setting the attenuation of the transmitter. |
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Alternative frequency setting in Hz. |
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Stopping the transmission. |
Advanced control and reset functions
| Name | Appointment |
|---|---|
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Reading the register of the functional module (IP core). |
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FIFOfootnote Target reset:[FIFO is a First In, First Out queue.] in the DFE system. |
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Resetting the auxiliary noise generator unit. |
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Resetting DMA Controllers note:[DMA (Direct Memory Access) — Direct memory access controller.] reception and transmission. |
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Resetting the receiving and transmitting DMA controllers. |
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Comprehensive FIFO buffer reset. |
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Writing to the register of the functional module (IP core). |
RF switches
| Name | The prototype | Appointment |
|---|---|---|
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Manual calibration of the feedback channel. |
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RF switching control on a hardware platform. |
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RF switching control on a hardware platform. |
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RF switching control on a hardware platform. |
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RF switching control on a hardware platform. |
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RF switching control on a hardware platform. |
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RF switching control on a hardware platform. |
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Enabling/disabling the duplication of transmitter data for MIMO modes. |
Data reception and transmission management
| Name | Appointment |
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Channel Attenuation Management ORX[2]. |
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Checking the completion of the DMA transmission for the main reception (RX) and feedback channels (ORX). |
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Checking the completion of the DMA transmission for the main reception (RX) and feedback channels (ORX). |
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Formatting received data from |
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Preparing complex data for transmission: scaling and interleaving of components. |
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Receiving data from the feedback channel (ORX) into RAM. |
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Initiates receiving data from the receiver into RAM. |
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Direct switching on/off of receiving channels. |
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The command to transfer data from RAM to the transmitter. |
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ORX channel attenuation management. |
Additional service functions
| Name | Appointment |
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Temperature monitoring of various components of the hardware platform. |
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Request the software version of the control module. |
Automatic gain control functions
| Name | The prototype | Appointment |
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Configuration of automatic gain control ( |
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Force the automatic gain control settings to be applied after they have been changed. |
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Reset the automatic gain control settings to the default values. |
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Enabling/disabling the duplication of transmitter data for MIMO modes. |
Networking and data exchange
The connection to the control module of the product is established via TCP protocol. The port number is fixed (12345). Function connect() it must be called before executing any control and data exchange commands. Breaking the connection is performed by the function disconnect() (or close(), if a synonym is used).
Sending control commands is implemented through a low-level function _send_command(), which transmits a string command and analyzes the response. The transmission and reception of binary data arrays are performed by the functions _put_data() and _get_data() according to the established exchange protocol.
SDR Registers
The table shows the register map of IP cores available through the mechanism. set_ip_core()/get_ip_core(). Addresses are given in hexadecimal format. The data types are given in accordance with the designations used in the FPGA project.
| IP Core | Address (hex) | Register Name | Data Type | Description |
|---|---|---|---|---|
DUCex[3] |
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Core Reset: Write |
DUCex |
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The unique time stamp of the core (format |
DUCex |
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The data register for setting the interpolation coefficient. |
DUCex |
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Turning the interpolator on/off. |
DUCex |
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Asynchronous core reset via AXI. |
DUCex |
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Global core activation. |
DUCex |
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Channel gain factor 0 (correction). |
DUCex |
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Enabling channel 0 gain. |
DUCex |
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Channel 1 gain (correction). |
DUCex |
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Enabling channel 1 gain. |
DUCex |
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Enabling NCO[4] channel 0. |
DUCex |
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NCO Channel phase increment 0 ( |
DUCex |
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The phase offset of the NCO channel is 0 ( |
DUCex |
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Resetting the NCO phase drive of channel 0. |
DUCex |
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NCO phase increment of Channel 1 ( |
DUCex |
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NCO phase offset of channel 1 ( |
DUCex |
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Reset the NCO phase drive of channel 1. |
DUCex |
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Enabling NCO channel 1. |
DUCex |
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Enabling DDS[5] channel 0. |
DUCex |
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Enabling DDS channel 1. |
DDCex |
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Core Reset: Write |
DDCex |
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The unique time stamp of the core (format |
DDCex |
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The data register for setting the decimation coefficient. |
DDCex |
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Switching on/off the decimator. |
DDCex |
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Asynchronous core reset via AXI[6]. |
DDCex |
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Channel gain factor 0 (correction). |
DDCex |
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Channel gain factor 1 (correction). |
DDCex |
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Enabling channel 0 gain. |
DDCex |
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Enabling channel 1 gain. |
DDCex |
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The increment of the NCO phase of the channel is 0. |
DDCex |
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The phase offset of the NCO channel is 0. |
DDCex |
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Resetting the NCO phase drive of channel 0. |
DDCex |
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The increment of the NCO phase of channel 1. |
DDCex |
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The NCO phase offset of channel 1. |
DDCex |
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Reset the NCO phase drive of channel 1. |
DDCex |
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Enabling the NCO of the common output. |
DDCex |
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Enabling NCO channel 1. |
DDCex |
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Enabling DDS channel 0. |
DDCex |
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Enabling DDS channel 1. |
DDCex |
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DDCex |
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DDCex |
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DDCex |
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DDCex |
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DDCex |
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DDCex |
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DDCex |
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DDCex |
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DDCex |
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DDCex |
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DDCex |
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AGCex[7] |
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Core Reset: Write |
AGCex |
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Enabling the kernel (enabled by default when bit 0 is equal to |
AGCex |
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The unique time stamp of the core (format |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the input port |
AGCex |
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The data register for the output port |
AGCex |
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The data register for the output port |
AGCex |
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The data register for the output port |
AGCex |
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The data register for the output port |
AGCex |
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The data register for the output port. |