Engee documentation

Technical description of the PS part

Description

In the context of systems-on-a-chip (SoC) of the Zynq UltraScale+ family, the abbreviation PS (Processing System, processor system) denotes a hardware subsystem of rigidly deterministic logic, which is a multi-core computing complex based on the ARM architecture.

ultrascale

The architecture of the RITM SDR USRP computing module is based on a heterogeneous system on a chip that combines two specialized processor domains to separate the tasks of control and signal processing in real time:

  1. Application Subsystem (Application Processing Unit, APU) This domain is implemented on the basis of a quad-core 64-bit general-purpose processor (ARM Cortex-A53 architecture).

    • Software environment: operates under the control of the Embedded Linux embedded operating system.

    • Purpose: to provide high-level network services and system administration. Within this subsystem, the server application of the PS-TCP interface and the MPM software package for UHD support are deployed. This layer is responsible for network connectivity, device parameter configuration, and SDR USRP RITM management.

  2. Real-Time Subsystem (Real-Time Processing Unit, RPU) The second domain is represented by a dual-core real-time processor (ARM Cortex-R5 architecture).

    • Software environment: The execution of the program code is carried out in the mode bare-metal (directly at the hardware level, without using the OS), which guarantees strict determinism of time intervals.

    • Purpose: Direct low-level control of the transceiver ADRV9009.