PFD
A frequency-phase detector (CFD) that compares the phase and frequency of two signals.
blockType: SubSystem
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Path in the library: |
Description
Block PFD generates two output pulses with different fill coefficients. The difference in fill factors is proportional to the phase difference between the input signals. In frequency synthesizer circuits, such as phase-locked frequency (PLL) systems, the block PFD compares the phase and frequency of the reference signal and the signal generated by the unit Ring Oscillator VCO, and determines the phase error.
Ports
Input
#
reference
—
frequency of the reference signal
scalar
Details
An input port that transmits a reference frequency to determine the phase error.
| Data types |
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| Complex numbers support |
I don’t |
#
feedback
—
frequency of the return signal
scalar
Details
An output port that transmits the frequency of the return signal to determine the phase error. In the PLL system, the output signal is Ring Oscillator VCO, passing through the clock frequency divider, comes back through the feedback port to PFD.
| Data types |
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| Complex numbers support |
I don’t |
Output
#
up
—
the transmitted frequency of the reference signal
scalar
Details
The output port transmitting the frequency of the reference signal. The difference in the fill factors of the signals in the up and down ports is proportional to the phase difference between the signals in the reference and feedback ports.
| Data types |
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| Complex numbers support |
I don’t |
#
down
—
the transmitted frequency of the return signal
scalar
Details
The output port transmitting the frequency of the return signal. The difference in the fill factors of the signals in the up and down ports is proportional to the phase difference between the signals in the reference and feedback ports.
| Data types |
|
| Complex numbers support |
I don’t |
Parameters
Parameters
# Deadband Compensation — delay added for active output near zero phase offset
Details
The delay added for the active output near the zero phase offset is given as a positive real scalar in seconds. The dead zone is a phase shift band near the zero phase shift, for which the output signal of the NFD is negligible.
| Default value |
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| Program usage name |
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| Tunable |
No |
| Evaluatable |
Yes |
# Enable increased buffer size — increasing the buffer size
Details
Check this box to enable buffer size increase during simulation. This will increase the size of the block buffer Variable Pulse Delay and Logic Decision inside the block PFD. This check box is unchecked By default.
| Default value |
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| Program usage name |
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| Tunable |
No |
| Evaluatable |
Yes |
# Buffer size — the number of input buffering samples available during the simulation
Details
The number of input buffering samples available during the simulation, specified as a positive integer scalar. This value sets the buffer size for blocks Variable Pulse Delay and Logic Decision inside the block PFD.
The choice of different simulation solvers or sampling strategies can change the number of input samples required to obtain an accurate output sample. Set the buffer size large enough so that the input buffer contains all the necessary input samples.
Dependencies
To use this option, select the check box Enable increased buffer size.
| Default value |
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| Program usage name |
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| Tunable |
No |
| Evaluatable |
Yes |
More detailed
Inside the mask
Details
Block PFD It consists of two synchronous D-triggers (D Flip-Flop). The reference and return signals coming to the corresponding ports serve as a trigger. The outputs of the two triggers pass through the NAND circuit, which serves as a reset signal. The pulse delay after the AND-NO circuit is introduced using the block Variable Pulse Delay to compensate for the dead zone.