Single Modulus Prescaler
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An integer clock frequency divider that divides the frequency of the input signal.
blockType: SubSystem
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Path in the library: |
Description
Block Single Modulus Prescaler divides the frequency of the input signal by a configurable integer value , which is transmitted to the div-by port. In frequency synthesizer circuits such as phase-locked frequency (PLL) systems, these pre-dividers divide the output frequency. Ring Oscillator VCO by an integer. The resulting lower frequency at the output port of the pre-divider is comparable to the reference signal at the input of the block PFD. A single-module pre-divider is also called an integer clock frequency divider.
Ports
Input
#
clk in
—
input clock frequency
scalar
Details
The input clock frequency, set as a scalar. In the PLL system, the clk in port is connected to the output port of the block Ring Oscillator VCO.
| Data types |
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| Complex numbers support |
I don’t |
#
div by
—
the ratio of output and input clock frequency
scalar
Details
The ratio of the output and input clock frequency, expressed as an integer scalar.
| Data types |
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| Complex numbers support |
I don’t |
Output
#
clk out
—
Output clock frequency
scalar
Details
The output clock frequency, expressed as a scalar. In the PLL system, the clk out port is connected to the feedback Input of the unit PFD. The output signal of the clk out port is a sequence of rectangular pulses with an amplitude of 1 V.
| Data types |
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| Complex numbers support |
I don’t |
More detailed
Inside the mask
Details
Block Single Modulus Prescaler It contains a subsystem of the integer clock frequency divider. Inside the subsystem, the trigger port monitors the rising edges of the input clock signal coming to the clk in port. The output pulse is given only after detection clock cycles. As a result, the input clock frequency is reduced by once.
