Wilkinson Power Divider (CE)
Modeling of ideal frequency-independent dividers or adders with S-parameters.
blockType: SubSystem
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Path in the library: |
Description
Block Wilkinson Power Divider (CE) Simulates power dividers or adders in a circuit envelope simulation environment as an S-parameter model. In a power divider, the input power enters one port, splits, and exits through different ports.
The matrix of S-parameters for the block Wilkinson Power Divider (CE) it looks like this:
For the DC carrier frequency (0 Hz) the Wilkinson power divider is a zero matrix.
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Ports
Conserving
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1+
—
the first electrical port
electricity
Details
The electrical RF port corresponding to the positive terminal of the Wilkinson divider.
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1−
—
the first electrical port
electricity
Details
The RF electrical port corresponding to the negative terminal of the Wilkinson divider.
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#
2+
—
the second electrical port
electricity
Details
The electrical RF port corresponding to the positive terminal of the Wilkinson divider.
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#
2−
—
the second electrical port
electricity
Details
The RF electrical port corresponding to the negative terminal of the Wilkinson divider.
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#
3+
—
The third electrical port
electricity
Details
The electrical RF port corresponding to the positive terminal of the Wilkinson divider.
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3−
—
The third electrical port
electricity
Details
The RF electrical port corresponding to the negative terminal of the Wilkinson divider.
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Parameters
Parameters
# Reference impedances, Ohm — divider reference impedance
Details
The reference impedance of the divider, set as a positive scalar or a three-element vector.
If the reference impedances of all ports are not equal, then the model inside the block Wilkinson Power Divider (CE) normalizes to 50 Om.
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| Default value |
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| Tunable |
No |
| Evaluatable |
Yes |