TCP (in terms of interaction with PS DMA)

The block diagram of the PS DMA TCP interaction is shown in the figure.

To ensure a continuous stream of IQ samples, DMA uses two different RAM: on PL for TX DMA and on PS for RX DMA.

The TX DMA block has a 128-bit output AXIS bus width, so two quadrature words are transmitted per clock cycle for two 16-bit DACs (16 bits × 2 IQ × 2 DAC × 2 words). The words are stored in RAM memory as follows:

The data passes through a fifo with 128 → 64-bit width conversion and through DUC, and then is converted using a converter from a sampling frequency of 491.52 MHz to 245.76 MHz with increasing bus width (this is necessary because the data at the JESD input must be in DDR format).

IQ samples from the ADC go a similar way in the opposite direction, taking into account that an AGC unit (AGCex) is installed on each receiving channel and data from JESD is received live without using DDR.