UHD

The block diagram of PL UHD is shown in the figure.

The 1G ethernet physical layer operates at a frequency of 125 MHz, SFP ethernet - 156.25 MHz. Network packets arrive at the physical layer data switch, then input packets are filtered in the UHD sfp_wrapper block: CHDR packets intended for RFNOC are pre-processed in the form of dropping ethernet/IP fields and sent to the UHD_core block. Other network packages, for example, broadcast for SDR search, log receipt requests via get_log_buf, ssh service packets and others are sent unchanged to DMA UHD. These packets are processed by the processor using the nixge driver (NI XGE Ethernet controller) and are used either by the UHD server or by the operating system/user.

The UHD_core block is the e320_core module from the standard E320 assembly based on the 1G project, containing the RFNOC key block, which in turn consists of:

The main logic of the unit operates at a frequency of 200 MHz, the control is at 40 MHz. The finished IQ output UHD_core samples with a 30.72 MHz band are interpolated by the DUCex IP core with a fixed interpolation factor of 16, converted to the 491.52 MHz band, and then sent to the transceiver via the TCP/UHD data switch and DDR converter. The received IQ samples from the transceiver go a similar way towards UHD_core, with the difference that the fixed decimation coefficient is 8. There are also AGC - AGCex blocks in the receiving path, one for each receiving channel.

The base addresses of the blocks are shown in the table.