Simple Dual Port RAM System

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A simple dual-port RAM that supports simultaneous read and write operations.

blockType: SimpleDualPortRAMSystem

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/Basic/Additional/Discrete/Simple Dual Port RAM System

Description

The Simple Dual Port RAM System block models a simple two-port random access memory (RAM) that supports simultaneous read and write operations. To configure this block, open it and set the value for the parameters Specify the type of RAM:

Single port - simulates a RAM that performs either a read or a write operation, depending on the signal on the wr_en port: a 1 value results in a write, a 0 value results in a read. When writing, two modes are available, depending on the value of the parameter Specify the output data for a write operation:
- Old data - the previous data is output to the output port and the new data is written instead;
- New data - the data from the input is repeated to the output port.
Simple dual port - simulates RAM with support for simultaneous read and write operations. Reads are performed continuously, writes are performed only upon an enable signal on the wr_en port. In the case when reading and writing occur at the same address, the read operation occurs before the write operation. The output always receives the result of the read operation.
Dual port - simulates RAM with support for simultaneous read and write operations. The key difference from the previous mode is the presence of two output ports. One always receives the result of a read operation and the other always receives the result of a write operation. Depending on the selected value of the parameter Specify the output data for a write operation (New data or Old data) the result of the operation is either new data written to the address or data that was stored at the address before the write operation. New data is written only when the enable signal on the wr_en port is present. If read and write operations are performed at the same address, the read operation comes before the write operation.

Limitations

A RAM address can be of fixed-point or integer data type, must be unsigned, and must be between 2 and 31 bits long.

Ports

Output

# rd_dout — data output from read address
scalar | vector

Details

Output data from read address rd_addr.

Dependencies

To use this port, set the parameters Specify the type of RAM to Simple dual port or Dual port.

Data types	`Float64`, `Float32`, `Float16`, `Int8`, `UInt8`, `Int16`, `UInt16`, `Int32`, `UInt32`, `UInt32`, `Int64`, `UInt64`, `Int128`, `UInt128`, `Bool`, `Fixed`
Complex numbers support	No

# dout — dout from read address
scalar | vector

Details

Output data from read address addr.

Dependencies

To use this port, set the parameters Specify the type of RAM to Single port.

Data types	`Float64`, `Float32`, `Float16`, `Int8`, `UInt8`, `Int16`, `UInt16`, `Int32`, `UInt32`, `UInt32`, `Int64`, `UInt64`, `Int128`, `UInt128`, `Bool`, `Fixed`.
Complex numbers support	No

# wr_dout — data output from the write address
scalar | vector

Details

Output data from the address to be written wr_addr.

Dependencies

To use this port, set the parameters Specify the type of RAM to Simple dual port or Dual port.

Data types	`Float64`, `Float32`, `Float16`, `Int8`, `UInt8`, `Int16`, `UInt16`, `Int32`, `UInt32`, `UInt32`, `Int64`, `UInt64`, `Int128`, `UInt128`, `Bool`, `Fixed`
Complex numbers support	No

Input

# din — recording data
scalar | vector

Details

Write data specified as a scalar or vector. You can write data to a RAM location if the write enable signal on the wr_en port is set to 1.

Data types	`Float64`, `Float32`, `Float16`, `Int8`, `UInt8`, `Int16`, `UInt16`, `Int32`, `UInt32`, `UInt32`, `Int64`, `UInt64`, `Int128`, `UInt128`, `Bool`, `Fixed`.
Complex numbers support	No

# wr_addr — write address
scalar | vector

Details

Write address specified as a scalar or vector. Use this address to write to RAM when the signal on the wr_en port is 1.

Dependencies

To use this port, set the parameters Specify the type of RAM to the value of Simple dual port or Dual port.

Data types	`UInt8`, `UInt16`, `Fixed`.
Complex numbers support	No

# wr_en — recording permission
scalar | vector

Details

Write resolution specified as a scalar or vector. When the signal on the wr_en port is 1, the block writes data to the specified memory location. In mode. Single port`mode, when the signal on the wr_en port is `0, the block reads the value from the memory location specified by the addr port. In other modes, the read operation takes place regardless of the signal on the wr_en port.

To use the column write method, the data type must be integer or fixed point.

Data types	`Int8`, `UInt8`, `Int16`, `UInt16`, `Int32`, `UInt32`, `Int64`, `UInt64`, `Int128`, `UInt128`, `Bool`, `Fixed`
Complex numbers support	No

# rd_addr — read address
scalar | vector

Details

A read address specified as a scalar or vector. Use this address to read from RAM. This value can be of fixed-point or integer data type, must be unsigned, and must be between 2 and 31 bits long.

Dependencies

To use this port, set the parameters Specify the type of RAM to Simple dual port or Dual port.

Data types	`UInt8`, `UInt16`, `Fixed`.
Complex numbers support	No

# addr — read or write address
scalar | vector

Details

Read or write address depending on the signal on the wr_en port: 1 is written, 0 is read.

Dependencies

To use this port, set the parameters Specify the type of RAM to Single port.

Data types	`UInt8`, `UInt16`, `Fixed`.
Complex numbers support	No

Parameters

Main

# Specify the type of RAM — RAM type
Single port | Simple dual port | Dual port

Details

RAM Type:

Single port - A single-port RAM that performs either a read or a write operation, depending on the signal on the wr_en port: a 1 value results in a write, a 0 value results in a read. The output is data from the read address addr.
Simple dual port - simple two-port RAM with write data, write address, write enable and read address as inputs and data from read address as output.
Dual port - true two-port RAM with write data a and b, write and read addresses for a and b, write enable a and b as inputs and data from write addresses a and b as outputs.

Values	`Single port` \| `Simple dual port` \| `Dual port`
Default value	`Simple dual port`
Program usage name	`RAMType`
Tunable	No
Evaluatable	No

# Specify the output data for a write operation — output data for a write operation
New data | Old data

Details

Specify the output data for the write operation:

Old data - output is performed on the output port of the previous data, in place of which the new data has been written;
New data - the data from the input is repeated to the output port.

Dependencies

To use this parameter, set the Specify the type of RAM parameters to Single port or Dual port.

Values	`New data` \| `Old data`
Default value	`New data`
Program usage name	`WriteOutputValue`
Tunable	No
Evaluatable	No

# Specify the RAM initial value — initial output data of the RAM simulation

Details

Specify the initial output data of the RAM simulation:

Scalar value.
A vector whose elements correspond to the initial values and RAM words.
A matrix by , whose elements correspond to the initial values and RAM words in RAM banks, where represents the number of RAM banks and represents the number of address locations in a RAM block, or vice versa.

Default value	`0`
Program usage name	`RAMInitialValue`
Tunable	No
Evaluatable	Yes

Usage of the column entry method for selective column entries

Details

You can use the column write method to treat RAM as a set of equally sized columns. During a write cycle, you can write to each of these columns individually. The data type and value of the write enable input and the data type of the write data input determine the size of each column and the columns to which the block writes an addressable memory location.

In this context:

- din write data input data type.
- input data width, which is equal to the value word length din.
- the data type of the write enable signal wr_en. This signal determines which columns the block writes to an addressable memory location. The block writes columns based on the 1s position in the binary representation of the wr_en value.
- the number of columns into which RAM space can be divided for writing data, which is equal to the word length of the wr_en value.
- width of each column, which is equal to .

The table shows the relationship between record input data types, record resolution input data types, the number of columns, and the width of each column.

bits

				bits
`UInt16`.	`16`	`Ufix4`	`4`	`4`
`UInt32	`32`	`Ufix4	`4`	`8`
`UInt64	`64`	`Ufix4	`4`	`16`
`UInt32	`32`	`UInt8	`8`	`4`
`UInt64	`64`	`UInt8	`8`	`8`
`Int32	`32`	`UInt16	`16`	`2`

UInt16.

16

Ufix4

4

`UInt32

32

`Ufix4

4

8

`UInt64

64

`Ufix4

4

16

`UInt32

32

`UInt8

8

4

`UInt64

64

`UInt8

8

`Int32

32

`UInt16

16

2

For example, if is UInt16 and is Ufix4, then is 16, is 4, and is 4 bits. If 980 is supplied to the din input, its binary representation is 0000001111010100. The column-wise representation of din is c4 = 0000, c3 = 0011, c2 = 1101, and c1 = 0100, where c1 is the first column.

The table shows the results of usage of the column-write method for different combinations of input data.

Value wr_en Binary representation wr_en Columns selected for writing to RAM Data in memory cell: before write operation Data in memory cell: after write operation dout

Value wr_en	Binary representation wr_en	Columns selected for writing to RAM	Data in memory cell: before write operation	Data in memory cell: after write operation	dout
`3`	`0011`	c2, c1	c4=`0000` c3=`0000` c2=`0000` c1=`0000`	c4=`0000` c3=`0000` c2=`1101` c1=`0100`	`212`
`4`	`0100`	c3	c4=`0000` c3=`0000` c2=`0000` c1=`0000`	c4=`0000` c3=`0011` c2=`0000` c1=`0000`	`768`
`6`	`0110`	c3, c2	c4=`0000` c3=`0000` c2=`0000` c1=`0000`	c4=`0000` c3=`0011` c2=`1101` c1=`0000`	`976`
`9`	`1001`	c4, c1	c4=`0000` c3=`0000` c2=`0000` c1=`0000`	c4=`0000` c3=`0000` c2=`0000` c1=`0100`	`4`
`9`	`1001`	c4, c1	c4=`1111` c3=`1111` c2=`1111` c1=`1111`	c4=`0000` c3=`1111` c2=`1111` c1=`0000`	`4084`

3

0011

c2, c1

c4=0000 c3=0000 c2=0000 c1=0000

c4=0000 c3=0000 c2=1101 c1=0100

212

4

0100

c4=0000 c3=0000 c2=0000 c1=0000

c4=0000 c3=0011 c2=0000 c1=0000

768

6

0110

c3, c2

c4=0000 c3=0000 c2=0000 c1=0000

c4=0000 c3=0011 c2=1101 c1=0000

976

9

1001

c4, c1

c4=0000 c3=0000 c2=0000 c1=0000

c4=0000 c3=0000 c2=0000 c1=0100

4

9

1001

c4, c1

c4=1111 c3=1111 c2=1111 c1=1111

c4=0000 c3=1111 c2=1111 c1=0000

4084

*``Limitations.

Inputs with signed data types and non-zero fraction lengths are not supported by the write enable input port.
The length of the write input data word must be a multiple of the length of the write enable word.

Simple Dual Port RAM System

Description

Limitations

Ports

Output

Input

Parameters

Main

Read More

Usage of the column entry method for selective column entries