General CRC Generator HDL Optimized

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Generates CRC code bits and appends them to the input data.

blockType: HDLCRCGenerator

Path in the library:

/Basic/Additional/Discrete/General CRC Generator HDL Optimized

Description

Block General CRC Generator HDL Optimized, which is similar to block General CRC Generator, generates cyclic redundancy check (CRC) bits and appends them to the input data. The General CRC Generator HDL Optimized block is optimised for HDL code generation. Instead of processing the entire frame at once, the block receives and returns a stream of data samples with accompanying control signals. The control signals indicate the validity of the samples and the frame boundaries. To achieve higher throughput, the block accepts vector data up to CRC length and implements a parallel architecture.

Ports

Input

# dataIn — input data
scalar | vector

Details

Input data:

scalar is an integer representing a number of bits. For this case, the block supports unsigned integers (UInt8, UInt16 or UInt32) or the fixdt(0,N,0) data type.
vector is a vector of binary values. For this case the block supports the Float64 or Bool data type.

The data width must be less than or equal to the CRC length, and the CRC length must be a multiple of the data width. For CRC-CCITT/CRC-16, the valid data width values are 16, 8, 4, 2, and 1.

Example: The vector input UInt8 is [0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1] equivalent to 19.

Data types	`Float64`, `UInt8`, `UInt16`, `UInt32`, `Bool`, `Fixed`.
Complex numbers support	No

# startIn — input frame start indicator
scalar

Details

Input frame start indicator.

Data types	`Bool`.
Complex numbers support	No

# endIn — input frame end indicator
scalar

Details

Indicator of the end of the input frame.

Data types	`Bool`.
Complex numbers support	No

# validIn — indicator of valid input data
scalar

Details

Indicator of valid input data.

This is a control signal that indicates whether the data on the dataIn port is valid.

Data types	`Bool`.
Complex numbers support	No

Output

# dataOut — output data
scalar | vector

Details

Output data with added checksum. The type and dimensionality of the output data are the same as the input data.

Data types	`Float64`, `UInt8`, `UInt16`, `UInt32`, `Bool`, `Fixed`.
Complex numbers support	No

# startOut — output frame start indicator
scalar

Details

Indicates the beginning of the output frame.

Data types	`Bool`.
Complex numbers support	No

# endOut — end of output frame indicator
scalar

Details

End of output frame indicator.

Data types	`Bool`.
Complex numbers support	No

# validOut — indicator of valid output data
scalar

Details

Indicator of valid output data.

This is a control signal that indicates whether the data on the dataOut port is valid.

Data types	`Bool`.
Complex numbers support	No

Parameters

# Polynomial — generating polynomial
Array of real numbers

Details

Define a generating polynomial as a binary vector with coefficients in descending order of degree. The length of the vector is equal to the degree of the polynomial plus 1.

Default value	`[1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1]`
Program usage name	`Polynomial`
Tunable	No
Evaluatable	Yes

# Initial state — initial states of the shift register

Details

Specify the initial states of the internal shift register as a binary scalar or vector. Usage of single and double precision numbers is allowed, but they must still be equal to either 0.0 or 1.0. For vector inputs, the initial state length must be equal to the degree of the generating polynomial.

Default value	`0`
Program usage name	`InitialState`
Tunable	No
Evaluatable	Yes

# Direct method — inclusion of a direct algorithm for checksum calculation
Logical

Details

Select this check box to use the direct algorithm to calculate the CRC checksum. If unchecked, the unit uses an indirect algorithm to calculate the CRC checksum.

For details about direct and indirect algorithms, refer to Direct and Indirect CRC Algorithms.

Default value	`false (switched off)`
Program usage name	`DirectMethod`
Tunable	No
Evaluatable	No

# Reflect input — input byte order
Logical

Details

Specify the order of the input bytes:

Select this check box to have the block flip each input byte before it enters the shift register.
Clear this check box to have the block transfer the message data to the shift register unchanged.

If checked, the input data width must be a multiple of 8.

Default value	`false (switched off)`
Program usage name	`ReflectInput`
Tunable	No
Evaluatable	No

# Reflect CRC checksum — checksum byte order
Logical

Details

Specify the order of the checksum bytes:

Select this check box to have the block flip each checksum byte before passing it to the final XOR stage.
Clear this check box so that the block passes the checksum byte to the final XOR stage unchanged.

If checked, the input data width must be a multiple of 8.

Default value	`false (switched off)`
Program usage name	`ReflectCRCChecksum`
Tunable	No
Evaluatable	No

# Final XOR value — checksum

Details

Specify the checksum as a binary scalar or vector. Usage of single and double precision numbers is allowed, but they must still be equal to either 0.0 or 1.0. The block performs an XOR operation on the CRC checksum with this value before adding it to the input data.

If you specify a vector input, the length of the vector must be equal to the degree of the generating polynomial.

Default value	`0`
Program usage name	`FinalXORValue`
Tunable	No
Evaluatable	Yes

Algorithms

When you use vector or integer input, the block implements the parallel CRC algorithm [1].

To ensure the high throughput of modern communication systems, the block implements the CRC algorithm with a parallel architecture. This architecture recursively computes CRC checksum bits for each input bit. At the end of the frame, the checksum result is appended to the message. For polynomial length recursive checksum computation for bits in parallel is as follows:

where

- is the matrix at , which selects the elements of the current state to compute the polynomial with the new input bits;
- is -element vector, which provides new input bits ordered with respect to the generating polynomial and filled with zeros;
- the block is realised using the logical AND;
- the block implements using logical XOR.

general crc generator hdl optimized 1 en

Literature

Campobello, G., G. Patane, and M. Russo. "Parallel Crc Realisation." IEEE Transactions on Computers 52, no. 10 (October 2003): 1312-19. https://doi.org/10.1109/TC.2003.1234528.