General CRC Generator HDL Optimized

Generates CRC code bits and adds them to the input data.

blockType: HDLCRCGenerator

Path in the library:

/Basic/Additional/Discrete/General CRC Generator HDL Optimized

Description

Block General CRC Generator HDL Optimized, which is similar to the block General CRC Generator generates control bits by cyclic redundancy check (CRC) and adds them to the input data. Block General CRC Generator HDL Optimized optimized for HDL code generation. Instead of processing the entire frame at once, the block receives and returns a stream of data samples with accompanying control signals. The control signals indicate the accuracy of the samples and the frame boundaries. To achieve higher throughput, the block accepts vector data up to CRC in length and implements a parallel architecture.

Ports

Input

# dataIn — input data
scalar | vector

Details

Input data:

scalar — an integer representing several bits. For this case, the block supports unsigned integers (UInt8, UInt16 or UInt32) or data type fixdt(0,N,0);
vector — a vector of binary values. For this case, the block supports the data type Float64 or Bool.

The width of the data must be less than or equal to the length of the CRC, and the length of the CRC must be a multiple of the width of the data. Acceptable data width values for CRC-CCITT/CRC-16 — 16, 8, 4, 2 and 1.

Example: Vector input UInt8 — [0, 0, 0, 1, 0, 0, 1, 1] equivalent to 19.

Data types	`Float64`, `UInt8`, `UInt16`, `UInt32`, `Bool`, `Fixed`
Complex numbers support	No

# startIn — input frame start indicator
scalar

Details

The indicator for the beginning of the input frame.

Data types	`Bool`
Complex numbers support	No

# endIn — end of input frame indicator
scalar

Details

The indicator for the end of the input frame.

Data types	`Bool`
Complex numbers support	No

# validIn — an indicator of acceptable input data
scalar

Details

An indicator of acceptable input data.

This is a control signal that indicates whether the data on the dataIn port is valid.

Data types	`Bool`
Complex numbers support	No

Output

# dataOut — output data
scalar | vector

Details

Output data with added checksum. The type and dimension of the output data are the same as the input data.

Data types	`Float64`, `UInt8`, `UInt16`, `UInt32`, `Bool`, `Fixed`
Complex numbers support	No

# startOut — output frame start indicator
scalar

Details

The indicator for the beginning of the output frame.

Data types	`Bool`
Complex numbers support	No

# endOut — output frame end indicator
scalar

Details

The indicator for the end of the output frame.

Data types	`Bool`
Complex numbers support	No

# validOut — acceptable output data indicator
scalar

Details

An indicator of acceptable output data.

This is a control signal that indicates whether the data on the dataOut port is valid.

Data types	`Bool`
Complex numbers support	No

Parameters

# Polynomial — generating polynomial
Array of real numbers

Details

Define the generating polynomial as a binary vector with coefficients in descending order of degrees. The length of the vector is equal to the degree of the polynomial plus 1.

Default value	`[1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1]`
Program usage name	`Polynomial`
Tunable	No
Evaluatable	Yes

# Initial state — initial states of the shift register

Details

Specify the initial states of the internal shift register in the form of a binary scalar or vector. The usage of single and double precision numbers is allowed, but they must still be equal to either 0.0, or 1.0. For vector inputs, the length of the initial state must be equal to the degree of the generating polynomial.

Default value	`0`
Program usage name	`InitialState`
Tunable	No
Evaluatable	Yes

# Direct method — enabling a direct checksum calculation algorithm
Logical

Details

Check this box to use the direct CRC checksum calculation algorithm. If unchecked, the block uses an indirect algorithm to calculate the CRC checksum.

For more information about direct and indirect algorithms, see Direct and indirect CRC algorithms.

Default value	`false (switched off)`
Program usage name	`DirectMethod`
Tunable	No
Evaluatable	No

# Reflect input — the order of the input bytes
Logical

Details

Specify the order of the input bytes:

check this box so that the block flips each input byte before it enters the shift register;
uncheck this box so that the block passes the message data to the shift register unchanged.

If the check box is checked, the width of the input data must be a multiple of 8.

Default value	`false (switched off)`
Program usage name	`ReflectInput`
Tunable	No
Evaluatable	No

# Reflect CRC checksum — checksum byte order
Logical

Details

Specify the order of the checksum bytes:

check this box so that the block flips each byte of the checksum before transferring it to the final XOR stage.;
uncheck this box so that the block transfers the checksum byte to the final XOR stage unchanged.

If the check box is checked, the width of the input data must be a multiple of 8.

Default value	`false (switched off)`
Program usage name	`ReflectCRCChecksum`
Tunable	No
Evaluatable	No

# Final XOR value — checksum

Details

Specify the checksum as a binary scalar or vector. The usage of single and double precision numbers is allowed, but they must still be equal to either 0.0, or 1.0. The block performs an XOR operation on the CRC checksum with this value before adding it to the input data.

If you specify a vector input, then the length of the vector must be equal to the degree of the generating polynomial.

Default value	`0`
Program usage name	`FinalXORValue`
Tunable	No
Evaluatable	Yes

Algorithms

When you use a vector or integer input, the block implements a parallel CRC algorithm [1].

To ensure the high throughput of modern communication systems, the block implements the CRC algorithm with a parallel architecture. This architecture computes recursively CRC checksum bits for each the input bit. At the end of the frame, the checksum result is added to the message. For polynomial length recursive checksum calculation for bits in parallel are as follows:

Where

— this is the matrix on , which selects the elements of the current state to calculate the polynomial with the new input bits;
— This is -an element vector that provides new input bits ordered relative to the generating polynomial and filled with zeros;
— the block implements using the logical AND;
— the block implements using logical XOR.

general crc generator hdl optimized 1 en

Literature

Campobello, G., G. Patane, and M. Russo. «Parallel Crc Realization.» IEEE Transactions on Computers 52, no. 10 (October 2003): 1312–1319. https://doi.org/10.1109/TC.2003.1234528.