Fractional Clock Divider with Accumulator
A clock frequency divider that divides the frequency of the input signal by a fractional number.
blockType: SubSystem
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Path in the library: |
Description
Block Fractional Clock Divider with Accumulator divides the frequency of the input signal by a configurable fractional value , which is transmitted to the div by port. Compared to the block Single Modulus Prescaler, block Fractional Clock Divider with Accumulator It helps to achieve a narrow channel spacing, which may be less than the reference frequency of the phase-locked frequency response (PLL) system.
Ports
Input
#
clk in
—
input clock frequency
scalar
Details
The input clock frequency, specified as a scalar. In the PLL system, the clk in port is connected to the output port of the block Ring Oscillator VCO.
| Data types |
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| Complex numbers support |
I don’t |
#
div by
—
the ratio of output and input clock frequency
scalar
Details
The ratio of the output and input clock frequency, specified as a fractional scalar.
The value on the port div by is divided into two parts: the whole part and the fractional part .
| Data types |
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| Complex numbers support |
I don’t |
Output
#
clk out
—
Output clock frequency
scalar
Details
The output clock frequency returned as a scalar. In the PLL system, the clk out port is connected to the feedback Input of the unit PFD. The output signal of the clk out port is a sequence of rectangular pulses with an amplitude of 1 V.
| Data types |
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| Complex numbers support |
I don’t |
#
state
—
recording a fractional missed pulse
scalar
Details
Recording of a fractional missed pulse. The value of the state port is increased by with each rising edge of the value clk out of the previous cycle. Whenever the port value of state exceeds 1, an overflow occurs, and the value of the carry port is set to equal 1.
| Data types |
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| Complex numbers support |
I don’t |
#
carry
—
activation of the pulse suppression function in case of port overflow state
0 (by default) | 1
Details
The output port that activates the pulse suppression function when the value on the state port overflows. Removing pulses is similar to dividing the input frequency by instead of .
| Data types |
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| Complex numbers support |
I don’t |
Parameters
Parameters
# Enable increased buffer size — increasing the buffer size
Details
Check this box to enable buffer size increase during simulation. This will increase the block buffer size Logic Decision inside the block Fractional Clock Divider with Accumulator. This check box is unchecked By default.
| Default value |
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| Program usage name |
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| Tunable |
No |
| Evaluatable |
Yes |
# Buffer size — the number of input buffering samples available during the simulation
Details
The number of input buffering samples available during the simulation, specified as a positive integer scalar. This value specifies the buffer size for the block Logic Decision inside the block Fractional Clock Divider with Accumulator.
The choice of different simulation solvers or sampling strategies can change the number of input samples required to obtain an accurate output sample. Set the buffer size large enough so that the input buffer contains all the necessary input samples.
Dependencies
To use this option, select the check box Enable increased buffer size.
| Default value |
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| Program usage name |
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| Tunable |
No |
| Evaluatable |
Yes |
Additional Info
Inside the mask
Details
Block Fractional Clock Divider with Accumulator It contains three subsystems: a fractional battery, a pulse suppression device and a block Single Modulus Prescaler.
When the unit first receives an input signal, the unit Single Modulus Prescaler divides the input signal into a whole part port values div by. Fractional part it is stored in the state port of the fractional accumulator subsystem.
The fractional accumulator subsystem updates the value of the state port with each rising edge received by the clk out port in the previous cycle. When the value of the state port exceeds 1, an overflow occurs, and the value output by the carry port changes to 1.
The carry port activates the pulse suppression device and removes one pulse from the clk in signal. It’s like dividing an input signal by a multiplier. , which allows you to get a common fractional division.
