Engee documentation

Discrete

Discrete FIR Filter HDL

A filter with a finite impulse response.

General CRC Generator HDL Optimized

Generates CRC code bits and adds them to the input data.

HDL Counter

Forward and countdown over a set range of numbers.

HDL FIFO

Storing a sequence of input samples in a first—in-first-out (FIFO) register.

Simple Dual Port RAM

Dual-port RAM with one output port.

Simple Dual Port RAM System

Simple dual-port RAM that supports simultaneous read and write operations.

Unit Delay Enabled Resettable Synchronous

Delays the input signal by one count when the external signal on the Enable port is true and the external signal on the Reset port is false.