Discrete Shift Register
Implementation of a shift register with serial input and parallel output.
blockType: SubSystem
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Description
Block Discrete Shift Register outputs a vector containing the latest N input signal counts. If more than one signal is received at the input, the unit outputs the last N samples of each signal in the following order:
Out = [u1(k), u1(k−1), u1(k−2), u1(k−3), u2(k), u2(k−1), u2(k−2), u2(k−3)]This example shows the output signal of a block for an input signal containing two signals, indicated by u1 and u2, and the number of counts N = 4, indicated by indexes from k before k − 3. The dimension of the output vector is 4 × 2 = 8.
Parameters
Main group
# Number of samples N: — number of counts
Details
Specify the number of samples (or steps) of the register. Minimum value — 1. By default — 32.
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Yes |
# Initial inputs: — the initial value of the samples
Details
Specify the initial value N − 1 counts preceding the moment in time 0. Enter a scalar or vector of the same size as the input signal.
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| Evaluatable |
Yes |
# Sample time: — interval between calculation steps
Details
Specify the block sampling period in seconds.
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| Evaluatable |
Yes |