Engee documentation

Enabled and Triggered Subsystem

A subsystem that is enabled and started by external input ports.

blockType: SubSystem

enabled and triggered subsystem

Path in the library:

/Basic/Ports & Subsystems/Enabled and Triggered Subsystem

Description

Block Enabled and Triggered Subsystem It is a pre-configured block. Subsystem, designed to create a subsystem that is enabled under the following conditions:

  • the switch-on control signal Enable has a positive value;

  • The trigger control signal Trigger has a trigger value.

enabled and triggered subsystem 1

For more information, see Triggered and Activated Subsystem.

Ports

Input

# In1 — the input signal to the subsystem
scalar | vector | the matrix

Details

Block placement In1 The subsystem adds an external input port. The port label matches the block name. In1.

Use blocks In1 to receive signals from the local environment.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

# Enable — the input signal controlling the unit
scalar

Details

Block placement Enable The subsystem adds an external input port Enable.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

# Trigger — trigger port
scalar

Details

Block placement Trigger The subsystem adds an external input port Trigger.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

Output

# Out1 — the output signal from the subsystem
scalar | vector | the matrix

Details

Block placement Out1 The subsystem adds an external output port. The port label matches the block name. Out1.

Use blocks Out1 to send signals to the local environment.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

  1. Practical work with model architecture in Engee

Additional options

C code generation: Yes

Verilog code generation: Yes