Engee documentation

While Iterator Subsystem

A subsystem that repeats execution during the current time step until the boolean expression is true.

blockType: SubSystem

while iterator subsystem

Path in the library:

/Basic/Ports & Subsystems/While Iterator Subsystem

Description

Block While Iterator Subsystem It is a pre-configured block. Subsystem, designed to create a subsystem that repeats execution during the simulation step until a logical condition is met. The execution is controlled by the block While Iterator inside the subsystem.

while iterator subsystem 1

Use blocks While Iterator Subsystem for modeling purposes:

  • an equivalent flowchart of the cycle while or do-while;

  • an iterative algorithm that converges to a more accurate solution after several iterations.

Ports

Input

# IC — the initial logical condition
scalar

Details

Block placement While Iterator connected to the block In1 in the subsystem block, adds this external input port to the block.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

# In1 — the input signal to the subsystem
scalar | vector | the matrix

Details

Block placement In1 The subsystem adds an external input port. The port label matches the block name. In1.

Use blocks In1 to receive signals from the local environment.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

Output

# Out1 — the output signal from the subsystem
scalar | vector | the matrix

Details

Block placement Out1 The subsystem adds an external output port. The port label matches the block name. Out1.

Use blocks Out1 to send signals to the local environment.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

  1. Practical work with model architecture in Engee

Additional options

C code generation: Yes

Verilog code generation: Yes