Engee documentation

While Iterator Subsystem

A subsystem that repeats execution during the current time step until the boolean expression is true.

blockType: SubSystem

Path in the library:

/Basic/Ports & Subsystems/While Iterator Subsystem

Description

Block While Iterator Subsystem It is a pre-configured block. Subsystem, designed to create a subsystem that repeats execution during the simulation step until a logical condition is met. The execution is controlled by the block While Iterator inside the subsystem.

while iterator subsystem 1

Use blocks While Iterator Subsystem for modeling purposes:

  • an equivalent flowchart of the cycle while or do-while;

  • an iterative algorithm that converges to a more accurate solution after several iterations.

Ports

Input

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Output

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Additional options

C code generation: Yes

Verilog code generation: Yes