Engee documentation

Enabled Subsystem

A subsystem whose execution is controlled by an external signal.

blockType: SubSystem

enabled subsystem

Path in the library:

/Basic/Ports & Subsystems/Enabled Subsystem

Description

Block Enabled Subsystem It is a pre-configured block. Subsystem, designed to create a subsystem that is activated by an external signal Enable. The subsystem is running while the external signal is positive (more 0).

enabled subsystem 1

Use the block Enabled Subsystem for modeling purposes:

  • gaps in the execution of blocks within the subsystem;

  • several enabled subsystems that are executed when these subsystems receive a positive control signal on the Enable ports.

For more information, see Activated subsystem.

Ports

Input

# In1 — the input signal to the subsystem
scalar | vector | the matrix

Details

Block placement In1 The subsystem adds an external input port. The port label matches the block name. In1.

Use blocks In1 to receive signals from the local environment.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

# Enable — the input signal controlling the unit
scalar | vector | the matrix

Details

Block placement Enable The subsystem adds an external input port Enable.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

Output

# Out1 — the output signal from the subsystem
scalar | vector | the matrix

Details

Block placement Out1 The subsystem adds an external output port. The port label matches the block name. Out1.

Use blocks Out1 to send signals to the local environment.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

  1. Practical work with model architecture in Engee

Additional options

C code generation: Yes

Verilog code generation: Yes