Engee documentation

Resettable Subsystem

A subsystem whose block status is reset when an external trigger is triggered.

blockType: SubSystem

resettable subsystem

Path in the library:

/Basic/Ports & Subsystems/Resettable Subsystem

Description

Block Resettable Subsystem It is a pre-configured block. Subsystem, designed to reset the subsystem by an external trigger. Block Resettable Subsystem It is executed at each time step, but conditionally resets the states of the blocks inside itself when a trigger event is triggered on the reset port. Reset. For more information about trigger events supported on the reset port, see Reset.

resettable subsystem 1

For more information, see Resettable Subsystem.

Ports

Input

# In1 — the input signal to the subsystem
scalar | vector | the matrix

Details

Block placement In1 The subsystem adds an external input port. The port label matches the block name. In1.

Use blocks In1 to receive signals from the local environment.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

# Reset port — the input signal controlling the unit
scalar | vector | the matrix

Details

Block placement Reset The subsystem adds an external input port Reset port.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

Output

# Out1 — the output signal from the subsystem
scalar | vector | the matrix

Details

Block placement Out1 The subsystem adds an external output port. The port label matches the block name. Out1.

Use blocks Out1 to send signals to the local environment.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

  1. Practical work with model architecture in Engee

Additional options

C code generation: Yes

Verilog code generation: Yes