Engee documentation

Triggered Subsystem

A subsystem whose execution is initiated by an external trigger signal.

blockType: SubSystem

triggered subsystem

Path in the library:

/Basic/Ports & Subsystems/Triggered Subsystem

Description

Block Triggered Subsystem It is a pre-configured block. Subsystem, designed to create a subsystem that is executed every time a control signal has a trigger value Trigger.

triggered subsystem 1

Use the block Triggered Subsystem for modeling purposes:

  • tasks that are performed when the trigger value is detected;

  • interrupts from I/O hardware;

  • a request from the processor to handle an exception or error.

For more information, see Triggered Subsystem.

Ports

Input

# In1 — the input signal to the subsystem
scalar | vector | the matrix

Details

Block placement In1 The subsystem adds an external input port. The port label matches the block name. In1.

Use blocks In1 to receive signals from the local environment.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

# Trigger — the input signal controlling the unit
scalar | vector | the matrix

Details

Block placement Trigger The subsystem adds an external input port Trigger.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

Output

# Out1 — the output signal from the subsystem
scalar | vector | the matrix

Details

Block placement Out1 The subsystem adds an external output port. The port label matches the block name. Out1.

Use blocks Out1 to send signals to the local environment.

Data types

Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool
Complex numbers support

No

  1. Practical work with model architecture in Engee

Additional options

C code generation: Yes

Verilog code generation: Yes