Verilog code generation from a model¶

This example uses the model from the following demonstration https://engee.com/helpcenter/stable/ru/interactive-scripts/base_simulation/PID_fixed.html, and given its use of fixed-point data types, we can afford to generate code from them in Verilog languages. We will generate the code from the PID-regulator block.

Now let's generate code in Verilog language from this model. To do this, set the attribute target="verilog" in the programme control function of the code generator.

Verilog is a hardware description language (HDL) used for designing and modelling digital systems such as FPGA and ASIC circuits. It allows the structure and behaviour of digital circuits to be described at the register and logic level, making it an essential tool for hardware engineers. Verilog supports parallel process modelling, which is critical for circuits with a large number of simultaneously operating components. The main applications of Verilog are listed below.

FPGA and ASIC design: Verilog allows you to describe complex digital systems, which can then be synthesised into physical circuits on FPGAs or integrated circuits.
Simulation and Verification: Verilog provides simulation capabilities, allowing you to test and debug circuits before implementing them in hardware.
development automation: synthesizers translate Verilog code into optimised logic circuits, simplifying the process of building and testing hardware components.

Verilog is used in projects requiring high-speed data processing and reliable parallel execution.

engee.generate_code("$(@__DIR__)/pid_fixed.engee", "$(@__DIR__)/verilog"; subsystem_name="SubSystem", target="verilog")

[ Info: Generated code and artifacts: /user/my_projects/Demo/Work/verilog/verilog

Now let's analyse the results.

As we can see, the code was successfully generated and can be used in further development, the code itself is presented below.

module pid_fixed_SubSystem(
  input clock,
                reset,
  input [15:0] io_setpoint,
                io_feedback,
  output [15:0] io_command
);

  reg [15:0] UnitDelay_state;
  wire [15:0] _AddAccum_T = io_setpoint - io_feedback;
  wire [28:0] _Gain_2_new_T_1 = {{13{_AddAccum_T[15]}}, _AddAccum_T} * 29'hA4;
  wire [29:0] _Gain_new_T_1 = {{14{_AddAccum_T[15]}}, _AddAccum_T} * 30'h6000;
  wire [15:0] _Add_1Accum_T = {_Gain_2_new_T_1[28:14], 1'h0} + UnitDelay_state;
  always @(posedge clock) begin
    if (reset)
      UnitDelay_state <= 16'h0;
    else
      UnitDelay_state <= _Add_1Accum_T;
  end // always @(posedge)
  assign io_command = _Gain_new_T_1[29:14] + {_Add_1Accum_T[15], _Add_1Accum_T[15:1]};
endmodule

Conclusion¶

In this example, we have looked at the code generation capabilities of Engee and shown you how to apply this tool to your projects.

Verilog code generation from a model¶

Conclusion¶

Blocks used in example¶