Counter

In this example, we will develop and test a counter model that supports Verilog code generation, as well as test its performance using a cloud compiler.

Let's start by analyzing the implemented model. This is a simple model made using basic blocks. It supports code generation, including a code generation template for a block of comparison operators. The generation template itself is presented below.

This code is a Chisel code generator designed to generate a block of a logical operator (for example, ==, !=, <, >). It uses built-in helper functions and labels (for example, //!, /*!) to generate the Verilog code.

The code is a step-by-step description of the block.

1. Definition of functions (block @Definitions)

show_chisel_type(x::typ)

Defines how to represent the type x in Chisel syntax:

• Bool() if it is a 1-bit boolean value.
• UInt(...) or SInt(...) if it is an integer type (without a fractional part).
• FixedPoint(...) if there is a fractional part (fixed point).

show_chisel_type(x::signal)
If the signal is an array (Vec), then returns Vec(n, base_type) Otherwise , just base_type.

2. Announcement of the output signal

val $(output(1)) = Wire($(show_chisel_type(output(1))))

Creates an output signal as Wire(...), the type of which is determined by the functions described above.

3. Generating the block body (block @Step)

patch_op(op)
Converts operators to Chisel syntax:

• "==" → "==="
• "~=" → "=/=" (inequality)

get_idx(len, blen)
It is used to access indexes in vector (massive) logic.:

• returns "" if is a scalar.
• (i) if the lengths match.
• (i % len) if broadcasting is required.

maybe_zext(sig, sig2)
If one of the signals is — unsigned And the other one — signed It may be required zext (zero expansion to a compatible format).

impl(sig1, sig2, op, out)
The main function of string generation:

• determines the size of the signals and their broadcast length;
• if necessary, it wraps in for- a cycle.
• generates an assignment of the form

output(i) := input1(i) <op> input2(i)

with processing zext, indexes and translation of operators.

This code implements a universal Chisel block generator for logical operations with support for vector signals, broadcasting, and type conversion. It is compiled into Chisel code for hardware description of blocks, for example, for FPGA or ASIC.

Next, let's look at the implemented model itself and its generation settings.

As we can see, the model is quite simple and has three input ports.:

1. the step with which the counter increment is performed;
2. the limit of the maximum allowable value of the counter;
3. Reset the counter.

Now that we've figured out the model, we'll generate its code and verify the resulting code based on the generated C function and based on the handwritten Verilog test bench, after adding a folder with compare.cgt en route Engee.

As we can see, the results of working with the code and the source model are identical, which indicates that the code generator is working correctly.
Now let's move on to writing a test binding of our generated code.

module count_Count(
input         clock,
              reset,
input  [31:0] io_Step,
              io_Limit_max,
input         io_Reset,
output [31:0] io_Cnt
);

reg  [31:0] UnitDelay_state;
wire [31:0] Switch =
  $signed(UnitDelay_state) > $signed(io_Limit_max) | io_Reset ? 32'h0 : UnitDelay_state;
always @(posedge clock) begin
  if (reset)
    UnitDelay_state <= 32'h0;
  else
    UnitDelay_state <= io_Step + Switch;
end // always @(posedge)
assign io_Cnt = Switch;
endmodule

module testbench;
reg clock;
reg reset;
reg [31:0] io_Step;
reg [31:0] io_Limit_max;
reg io_Reset;
wire [31:0] io_Cnt;

// Instantiate the module under test
count_Count dut (
  .clock(clock),
  .reset(reset),
  .io_Step(io_Step),
  .io_Limit_max(io_Limit_max),
  .io_Reset(io_Reset),
  .io_Cnt(io_Cnt)
);

// Clock generation
always 5 clock = ~clock;

// Test sequence
initial begin
  // Initialize signals
  clock = 0;
  reset = 1;
  io_Step = 3;
  io_Limit_max = 27;
  io_Reset = 0;
  
  // Display header
  $display("tStep\tLimit\tCnt");
  $monitor(io_Step, io_Limit_max, io_Cnt);
  
  // Apply reset
  10 reset = 0;
  
  // Run simulation until counter wraps around
  200;
  $finish;
end
endmodule

Module testbench It is intended for checking the operation of the counter. Below we list the actions that he performs.

1. Initializes the signals:
   • clock = 0;
   • reset = 1;
   • io_Step = 3;
   • io_Limit_max = 27;
   • io_Reset = 0.
2. Generates a clock signal with a period of 10 clock cycles.
3. Deactivates the signal after 10 clock cycles reset.
4. Outputs values io_Step, io_Limit_max and io_Cnt to monitor the behavior of the counter.
5. Completes the simulation after 200 clock cycles.

Now let's run our test using the JDoodle Verilog Online website. It is a convenient online platform for writing, compiling and running Verilog code directly in the browser.

Conclusion

The simulation results indicate that the code is working correctly.
And it is similar to the results obtained in the model. This means that the generated counter can be used in FPGA operation.