Unit Delay
Delay the signal by one calculation step.
Description
The Unit Delay block delays input by the specified calculation step. When placed in an iterator subsystem, it delays the input by one iteration. This block is equivalent to the discrete time operator . The block takes one input signal and generates one output signal. Each signal can be scalar or vector. If the input signal is a vector, the block delays all elements of the vector for the same computation step.
The block output for the first time step is specified by the Initial conditions parameter. Correct choice of this parameter can minimise undesirable behaviour of the output signal. The calculation step is set by the Sample time parameter. The value -1 means that the block inherits the value of the calculation step.
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The block will generate an error if you use it to create a transition between blocks operating at different sampling rates. Instead, use the block Rate Transition. |
Comparison with similar blocks
The Memory, Unit Delay and Zero-Order Hold blocks provide similar functionality but have different features. In addition, the purpose of each block is different.
The table shows the recommended usage for each block.
| Block | Block Purpose |
|---|---|
Unit Delay. |
Realises a delay using the specified calculation step. The block accepts and outputs signals with discrete calculation step. |
Realises a delay using one basic calculation step. Ideally, the block accepts continuous (or fixed with a small time step) signals and outputs a signal that is fixed with a small time step. |
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Converts a continuous input signal to a discrete signal. |
Each unit has the following capabilities.
| Capability | Memory | Unit Delay | Zero-Order Hold |
|---|---|---|---|
Initial condition setting |
Yes |
Yes |
No, because the block output at time |
Setting the calculation step |
No, because the block can only inherit the calculation step from the control block or solver used for the whole model. |
Yes |
Yes |
Support for frame-based signals |
No |
Yes |
Yes |
Support for status logging |
No |
Yes |
No |
Ports
Input
Port_1 - input signal
scalar | vector | bus
Input signal, which the block delays by one calculation step. Defined as a scalar, vector or bus.
For more details on working with custom bus type, see here.
Data types: Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool, BusSignal.
Support for complex numbers: Yes
Output
Port_1 - output signal
scalar | vector | bus
Output signal, i.e. input signal delayed by one calculation step. It is specified as a scalar, vector or bus. The output signal type corresponds to the input signal type.
For more details on working with custom bus type, see here.
Data types: Float16, Float32, Float64, Int8, Int16, Int32, Int64, UInt8, UInt16, UInt32, UInt64, Bool, BusSignal.
Support for complex numbers: Yes
Parameters
Main
Initial condition - block output at the first step of calculation
0 (by default) | scalar | vector | N-dimensional array | bus
The block output at the first step of the calculation, during which the output of the Unit Delay block is otherwise undefined.
Block parameter |
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Values |
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By default |
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Sample time (-1 for inherited) - interval between calculation steps
-1.0 (by default) | scalar
Specify the interval between calculation steps as a non-negative number. To inherit a calculation step, set this parameter to -1.
Block parameter |
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Values |
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By default |
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