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JK Trigger Model

In this example, we will show how to model a JK trigger using components from the basic palette of the block library.

Model description

This model shows how to assemble a JK trigger from logic components (blocks Logic) and delay blocks (UnitDelay). The trigger updates its state with each pulse of the clock signal (block PulseGenerator), so this model can be used to show how the input signal is generated depending on the switching of the J and K inputs.

If the input switches of the model are in the initial state (up position) both JK inputs of the trigger are set to 1, and then the output state of the trigger is switched on each falling edge of the clock signal (back edge).

image.png

There are two SR triggers inside the JK trigger subsystem:

image.png

SR triggers look as follows (all logic elements are implemented using Logic blocks ):

image.png

The upper block Unit Delay is initialised with the value -1 before the output Q, the lower output is initialised with zero.

Model operation

Let's load (if the model is not already open) and execute the model by means of progamma control:

In [ ]: 
if "jk_trigger" ∉ getfield.(engee.get_all_models(), :name)
    engee.load( "$(@__DIR__)/jk_trigger.engee");
end;

data = engee.run( "jk_trigger" )
Out[0]:
SimulationResult(
    "Q" => WorkspaceArray("jk_trigger/Q"),
    "J" => WorkspaceArray("jk_trigger/J"),
    "CLK" => WorkspaceArray("jk_trigger/CLK"),
    "~Q" => WorkspaceArray("jk_trigger/~Q"),
    "K" => WorkspaceArray("jk_trigger/K")
)

Plot the model in the state when both inputs are set to the upper position.

In [ ]: 
gr()

plot(
    plot( data["CLK"].time,
        [ data["CLK"].value, data["J"].value, data["K"].value ],
          lc=[1 2 5], lw=2, titlefont=font(9), linestyle=[:solid :solid :dash], legend = :outerright,
          label=["CLK" "J" "K"], title="Сигналы на входе синхронного JK триггера"),
    plot( data["CLK"].time,
          [ data["Q"].value, data["~Q"].value ],
          lc=[3 4], lw=2, legend = :outerright, titlefont=font(9),
          label=["Q" "~Q"], title="Сигналы на выходе синхронного JK триггера"),
    layout=(2,1)
)
Out[0]:

When the clock signal CLK is in the up position, the first RS-trigger is activated and the second one is not. The signals J and K can change the value of the first trigger at this time, while the value of the second trigger is frozen. If you change the input parameters by setting J=1 and K=0, the output of the first trigger Q is set to 1, but the input of the second trigger is not changed.

As soon as the clock signal CLK goes low, the second RS trigger is activated and the first trigger is disabled. The second trigger assumes the state of the first trigger, its output values are now equal to the output values of the first trigger in the previous step (the first trigger retains its previous state). The output of the first trigger was Q=0, so the second trigger receives S=1 and R=0 as input, and the output of the second trigger becomes Q=1. But since the input trigger is disabled, changing the signals at the input does not change its state.

And when the clock signal CLK goes high again, the first trigger is activated and the second trigger is disabled. The outputs of JK trigger do not change on the rising edge because the second trigger is disabled and does not change its state.

Conclusion

We have studied the model of a JK-trigger, a device capable of staying in one of two stable states for a long time and alternating them under the influence of external signals.

A more detailed model could be built from CMOS logic blocks, but in its current form it perfectly shows the principle of JK-trigger operation.

Blocks used in example