Construction of truth tables, Boolean schemes and expressions¶
In this demo we will show how to create a discrete model to calculate output signals from a truth table and compare it with a model created from logic elements.
Model description¶
Let's create a model that converts a set of bits at the input to a signal at the output generated according to the following truth table:
| A | B | C | Y |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
A truth table can be defined in many different ways, for example by using the code inside the block Engee Function.
Input signals are generated using pulse generators Pulse Generator, each next generator has a pulse period divided by 2 ( the "youngest" generator has a period 1 с, the next 2 с, the "oldest" - 4 с) . By default, all generators at the zero moment of time start from the upper pulse level (specified in the parameter Amplitude). The familiar form for truth tables implies that the enumeration of signals starts from the lower level. To avoid changing the phase of each oscillator, we apply the operation Not to each input channel (using the appropriately configured block Logical Operator).
The sampling step of the model is equal to 0.5. Each oscillator for one full period produces both pulse values - upper and lower, with a fill factor of 50%. And so we get the following model:
Inside the block, the truth table is described by the following code:
function (c::Block)(t::Real, A, B, C)
if A == 0 && B == 0 && C == 0 return 0;
elseif A == 0 && B == 0 && C == 1 return 0;
elseif A == 0 && B == 1 && C == 0 return 1;
elseif A == 0 && B == 1 && C == 1 return 0;
elseif A == 1 && B == 0 && C == 0 return 1;
elseif A == 1 && B == 0 && C == 1 return 0;
elseif A == 1 && B == 1 && C == 0 return 1;
elseif A == 1 && B == 1 && C == 1 return 0;
else return 0; end;
end
We can create the same circuit using AND, OR, NOT logic elements.
Our truth table corresponds to the equation described by the formula $F = (A \lor B) \land (\lnot C$). It can be easily implemented using several blocks Logical Operator.
Or by using the expression (u[1] || u[2]) && !u[3] inside the block Fcn.
Running the model¶
Let's run the model using the software control commands:
modelName = "truth_tables"
# Если модель еще не открыта, загрузим из файла
if modelName ∉ [m.name for m in engee.get_all_models()] engee.load( "$(@__DIR__)/$modelName.engee"); end;
data = engee.run( modelName )
And visualise the result. If the transformation of the truth table into a logic diagram is done correctly, we should get three identical graphs:
gr()
plot(
plot( data["Y"].time, data["Y"].value, st=:step, lc=1, leg=false, title="Сигналы по таблице истинности" ),
plot( data["Y1"].time, data["Y1"].value, st=:step, lc=2, leg=false, title="Сигналы по логической схеме" ),
plot( data["Y1"].time, data["Y2"].value, st=:step, lc=3, leg=false, title="Сигналы по логическому выражению" ),
layout=(3,1)
)
Conclusion¶
We have built some simple models that can serve to study microelectronics or to create an environment for testing digital devices.