Engee documentation

What’s new in 25.11

_ Release Date: November 2025_

rn main User experience

n new L-Card 502 Support Package

We have fully completed the development of the L-Card L-502 module support package. The support package enables Engee to work with the L-502 ADC/DAC module using the L-CARD L-502 library blocks. The package runs on top of the subsystem Engee.Integrations and provides access to the analog and digital inputs/outputs of the L-Card modules.

For more information, follow the link: L-Card L-502 Module Support Package.

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rn mod The modeling environment

i important Steady-state support for Load Flow Source

Steady-state option for the block Load Flow Source It makes it possible to calculate the electric power regime in dynamic models in Engee. The user can configure the roles of sources and loads implemented by the Load Flow Source blocks in the model when operating in the steady-state mode of the electric power grid. In this case solver Engee automatically calculates the operating mode of the circuit and starts the model from this mode without transients at the initial time.

In addition, we have significantly improved the reliability of the algorithm for calculating the non-sinusoidal steady-state for all physical models.

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u update Unsaved changes in the mask editor

Now Engee will visually (with an asterisk) show if in xref:guide/masks-main.adocThere are unsaved changes in the block mask editor. No more anxiety: you know exactly when to save your job!

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n new Hide or show the name of individual model blocks

They made it possible to individually customize the display of the name for each block. This will allow you to customize the appearance of the model even more flexibly and will be useful when debugging models.

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u update Hide or show the name of individual model blocks

Improved the behavior of charts when closing and opening models. Previously, by default in the window signal visualization graphs icon 1 An empty chart was always opened, even if it was deleted. Now, if the chart in the model was deliberately closed, then when it is reopened, it will not reopen.

u update Changed the logic of port allocation on the block side

The logic of allocating a large number of ports on the block side has been optimized. Firstly, it has become more beautiful, and secondly, we have solved the problem of signal micro-faults with a large number of ports.

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rn blocks New blocks and updates

rn so func Library updates and fixes

Signal processing

System objects:

Functions:

RF components


rn codegen Code generation

n new Support for models with implicitly specified sampling rates

Models can contain blocks operating at different sampling frequencies (with different calculation steps). If these frequencies are not multiples, then an additional, implicit sampling frequency is introduced into the model. It represents the largest common divider of the sampling frequencies present in the model. Now the code generator supports such models and correctly generates the base sampling rate (minimum calculation step) for the model.

n new Support for mask parameters for code generation

The masked blocks containing the mask parameters are now supported by the code generator. The behavior of the code generator will differ depending on the selected "Default Parameter Behavior" setting (Built-in or Configurable).

Additional information is available in the documentation.: Parameters of masked blocks.

n new Improved automatic naming of variables in code

Now the names of model elements such as subsystems, signals, blocks, block parameters, and block mask parameters are generated with more logical and consistent names. This helps to improve the readability of the code and eliminate possible collisions of variable names in the generated code.

Additional information is available in the documentation.: Rules for naming variables in the generated code.

n new Enabled Subsystem support for Verilog generation

Now the block Enabled Subsystem is supported for Verilog code generation. In the block documentation, we talked in more detail about the aspects of generating Verilog code from the Enabled Subsystem.: Verilog Generation.


rn edm Hardware support, interfaces, and external integrations

n new Functions for working with sockets on the client program side

Now in the subsystem Engee.Integrations A support package for sockets is available. This allows you to work more flexibly with raw sockets than with existing support packages for TCP/IP and UDP.

Additional information in the documentation: Sockets Support Package.

u update Updates and fixes in the Hardware block library

We regularly update and improve the blocks in the category "Hardware". Install an up-to-date support package to enjoy the latest features: Hardware connection.


rn ritm Running models on rhythm

n new Support for the RHYTHM Spectrum block

A block has appeared in the RHYTHM block library that allows you to visualize the signal spectrum. This expands the visualization capabilities on the KPM RHYTHM screen.

u update Updates and fixes in the RHYTHM block library

We regularly update and improve the blocks in the category "RITM". Install an up-to-date support package to enjoy the latest features: RITM KPM Support Package.